469 Commits

Author SHA1 Message Date
ikari
858d660569 Update a slew of Xilinx autogenerated files 2025-06-24 10:58:46 +02:00
ikari
2474621d5f S-DD1: support "mixed mapper" SRAM mapping
Both "HiROM" and "LoROM" style mapping are supported by S-DD1.
Also remove redundant code and connections for address decoder.
2025-06-24 10:56:38 +02:00
ikari
c56a942f9a Adjust file timestamps for SmartXPlorer runs
prevents unnecessary re-running of SmartXPlorer targets in Makefile
2025-06-22 19:52:22 +02:00
ikari
6fa3200ff8 Improve Xilinx legacy tool compatibility 2025-06-22 19:39:10 +02:00
ikari
56dd166f37 Revert pulse end strobe based time sharing
Seems to have caused problems on a number of units; reverting until further analysis/refinement
2024-07-04 22:28:54 +02:00
ikari
f759f6047f SuperFX: Revert to previous bus sampling timing
This seems to have caused random access glitches for the GSU core.
2023-08-21 11:28:16 +02:00
redguyyyy
649c528ae6 Fixed branch latency and readjusted memory latencies which were
compensating for it.
Added some performance counters available in DEBUG mode.
2023-06-21 12:26:45 +02:00
redguyyyy
98cee5d998 Fixed CTX DMA write snoops in CT by blocking concurrent PARD assertion. 2023-04-12 17:00:52 +02:00
Maximilian Rehkopf
5b0f22d411 Ensure MSU-1 data address increment at end of DMA (#208)
* Ensure MSU-1 data address increment at end of DMA

* fix MSU1 address increment for rest of the FPGA cores

* update generated files
2023-03-30 11:09:25 +02:00
redguyyyy
1a071bbd8a Added CCNT_RESB (wait bit) implementation. Halts SA-1 instruction execute
after last completed op without redirection to reset vector on resume.
No known use in commercial games.
2023-03-07 22:35:36 +01:00
redacted173
dce71ed43b Fix for SGB controller multitap on SD2SNES mk2 (classic) (#168) 2023-02-16 09:37:50 +01:00
ikari
7ee1d5554d SA-1 quick fix: increase execution speed (1.10.0 regression) 2023-02-16 08:37:44 +01:00
ikari
e9a11762d9 FPGA: General update of generated files 2023-02-03 01:37:32 +01:00
ikari
fcc1d78923 FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz
Required to support STM32 clock output (MCO1) which cannot be fed and
prescaled from the CPU clock
2023-02-03 01:37:31 +01:00
ikari
c3dc4d5bff FPGA: fix occasional crash on save/load state
Savestate hook requires re-entry from NMI/IRQ, but lack of detected button
presses can preempt that and jump back to the game instead, corrupting
the stack and disrupting savestate hook execution flow.

A force_entry flag is added that is set when the FPGA enables the branch
to the savestate handler, and does not disable it before hook mapping
is disabled by the unlock_disable register ($2BFD).
2023-02-03 01:37:31 +01:00
ikari
96d8e1ab1c FPGA: Add support for running XILINX tools via WSL2 2023-02-03 01:37:31 +01:00
redacted173
fe15b2f3a2 Misc SGB notes and fixes (#153)
* - Fixed missing line 0 OAM STAT interrupt.

* - Added some notes.

* - Added support for (non save state) MCU write of SC to assert interrupt
request.

* - Removed trailing white space from several files and updated some
comments.

* Updated notes.

Co-authored-by: Your Name <youremail@yourdomain.com>
2021-08-02 18:18:48 +02:00
ikari
9cdb5df25e Merge remote-tracking branch 'github/develop' into develop 2021-07-30 17:11:18 +02:00
ikari
9e905ab267 [FPGA/test] update initial values and edge detection from base core 2021-07-30 12:35:18 +02:00
ikari
e35792e068 FPGA: Bump Quartus version, update generated files 2021-07-29 23:06:25 +02:00
ikari
904a9c42aa [FPGA/GSU] correct NMI/IRQ vector injection cycle count 2021-07-29 22:21:29 +02:00
ikari
57797f341f FPGA: fix ROM address detection to exclude WRAM
(simply use /ROMSEL from SNES instead of manual decoding)
2021-07-28 11:09:49 +02:00
ikari
f7e1208b06 comments, wording, cleanup, cosmetics 2021-07-28 02:19:06 +02:00
ikari
26e9f2cc3b FPGA: update auto region patch state machine for all cores 2021-07-28 02:07:10 +02:00
ikari
81c58ee516 SGB: add dedicated MSU1 build for sd2snes Mk.2 2021-07-28 01:54:15 +02:00
ikari
83f71ded0f FPGA build: add support for differing source paths 2021-07-28 01:52:25 +02:00
ikari
91acf7c843 FPGA build: fix hardcoded paths 2021-07-28 01:28:26 +02:00
ikari
90b833732d FPGA build: fail when timing not met 2021-07-28 01:27:47 +02:00
ikari
395ae09084 FPGA build: add header files to prerequisites 2021-07-28 01:26:42 +02:00
ikari
69fb329172 BS-X: flash access may not override in-game hook bank access 2021-07-28 01:13:32 +02:00
ikari
008d4e3efe Give full access to banks C0-FF during in-game hook
This allows for savestate handler execution directly from the menu ROM
bank without having to copy it to block RAM or similar.
(this seems to be causing unresolvable issues with HDMA interrupting
NMI/IRQ so it will be due for an overhaul)
2021-07-28 00:51:33 +02:00
ikari
421725dec9 DSPx: get up to date with base core
(relocatable save ram area, unlockable banks E0-FF, USB EXE hook...)
2021-07-28 00:40:52 +02:00
ikari
031cb5201d integrate savestate handler call with in-game hook
Also move in-game hook out of the way of MCU_CMD area used by savestates
2021-07-28 00:30:48 +02:00
ikari
f5498c8d6b Savestates: Do not attempt to snoop anything coming from cart
Databus direction was reversed according to the ROMSEL signal, not
taking into account SRAM that is mapped outside of active ROMSEL areas.
Instead take into account anything where data is sourced from the
cartridge (ROM_HIT).
2021-07-22 14:07:09 +02:00
ikari
0a165d0235 Savestates: do not snoop SNES native PA registers
Only snoop registers 2100-2183 and ignore the ones we supply ourselves.
e.g. Trying to snoop BS-X registers would result in the SNES not being
able to read them at all, freezing the
BS-X BIOS at the startup screen.
2021-07-22 13:57:34 +02:00
ikari
d31295a091 [FPGA/DSP] Deassert write enable one clock before address change 2021-07-22 12:43:21 +02:00
ikari
3348f3e057 [FPGA/DSP] update save state logic, add source files 2021-07-22 12:16:45 +02:00
ikari
6b1a4254b1 FPGA: Mask data line toggling before data ready
On some occasions data output can be enabled before data is valid.
This results in needless data line toggling which in turn can cause
coupling into other signals, thereby potentially altering the ROM address
and putting wrong data on the bus, etc.
Use a narrowed output enable signal for SNES read cases to prevent this
effect.
2021-07-20 23:14:36 +02:00
ikari
3ccffb1fda Detect end of cycle based on longest enable pulse
CPU_CLK is substantially shorter than RD# during DMA transfers.
Access cycle end was previously based on falling edge of CPU_CLK.
This resulted in premature yielding of RAM access to the bus and in
consequence incorrect values leaking onto the bus.
2021-07-20 18:19:18 +02:00
Thomas Prescott
195e1211a6 update msu-1 revision on the other fpga cores 2021-06-15 18:37:17 -05:00
Thomas Prescott
802fc51d0f fpga_base: change MSU-1 chip revision to 2 (#151) 2021-06-14 00:33:08 +02:00
ikari
d7f4bd7439 Speed up Xilinx builds (eliminate xtclsh "Process Run")
Xilinx command line tools (xst, par, map ...) block on console output when
run via the Tcl shell's "Process Run" command which seems to flush the
console about once per second. Running he command line tools directly
from the shell results in much faster output and thus operation of the
tools. However in order to extract the command line parameters for the
tools from the ISE project file it becomes necessary to mimic some of
the internal scripting. Tcl scripts are added that are run via xtclsh to
output parameters that are then passed to the command line tools for
direct execution.
2021-02-19 10:08:32 +01:00
ikari
73a034238e FPGA Makefile: show build status in window title 2021-01-19 13:13:46 +01:00
ikari
6759ce7277 Update global & FPGA makefiles
avoid redundant rebuilding of FPGA cores
2020-10-20 23:15:54 +02:00
ikari
cd151f3904 Comments, formatting, cleanup 2020-10-16 02:08:44 +02:00
ikari
346b5f02c7 FPGA_base: relax address decoder timing 2020-10-16 01:40:46 +02:00
ikari
33699060c1 RTC: relax DOW calculation (add intermediate states) 2020-10-16 00:06:57 +02:00
ikari
7263930222 Merge branch 'develop' into furious-save3 2020-09-30 18:06:11 +02:00
ikari
90d2d13009 Merge branch 'savestate' of https://github.com/furious/sd2snes into furious-save2 2020-09-30 17:49:41 +02:00
ikari
e16b007525 Misc cleanup+whitespace 2020-09-29 22:13:15 +02:00