469 Commits

Author SHA1 Message Date
ikari
5d5e918fb0 Fix timing for auto region patching 2018-12-08 23:15:45 +01:00
ikari
87403fb370 Adjust PAWR sampling point on 96MHz cores for brightness patch 2018-12-08 23:13:31 +01:00
ikari
bfc82ba830 Whitespace/general cleanup 2018-11-05 00:29:05 +01:00
ikari
ac546fb7fa Fix brightness patching for DMA and SA1 IRAM 2018-11-03 01:01:20 +01:00
RedGuyyyy
26c54c7738 Fixed messy space/tab formatting in ctx block. 2018-10-02 18:38:24 -07:00
RedGuyyyy
e94d0f172e Fixed terrible bug that created a race between initial context state and the initial clear. 2018-09-25 19:21:44 -07:00
RedGuyyyy
be3de6747f Fixed exe region bug when applied in the menu. 2018-09-23 21:11:45 -07:00
RedGuyyyy
396a25f3ba Added branch for usb changes.
Merged with 1.8.0+.
Updated save state patch to use exe hook.  Patch must be re-applied if non-base FPGA is loaded.  Only works on base FPGA file.
Fixed bug in exe portion to support reentrant code.
Removed development features in the FPGA (streaming/buffer changes).
Added back MSU and DSP to main FPGA file.
2018-09-23 17:09:59 -07:00
RedGuyyyy
158cdb4416 Added menu option for reset hook patch.
Fixed dead timeout delay to match frequency.
2018-09-10 19:02:20 -07:00
RedGuyyyy
5dfad7b12e Added (untested) auto mode for vbd. 2018-09-07 19:55:18 -07:00
RedGuyyyy
0ec6304d1b Added sa1 branch based off of develop.
Fixed led brightness assignment in main outer loop.
2018-09-04 08:08:44 -07:00
ikari
da99d6fe32 Disable Satellaview emulation when original base unit is detected 2018-09-03 21:56:23 +02:00
RedGuyyyy
c2c90d00b5 Added missing reset for psram access signal.
Added qualifiers for gsu_enable bus OE.
Removed commented out code.
2018-08-08 13:44:46 -07:00
Maximilian Rehkopf
872300caa4 Fix menu lockup after reconfiguration (databus glitch)
To support multiple custom chips the FPGA is reconfigured at ROM loading
time while the menu is running.

After reconfiguration the initial state of all synchronizing shift
registers was 0 which led the FPGA to believe the SNES is actively
accessing the bus, writing to peripheral address $00 (CPU address $2100
- brightness register). This invalid state persists for a couple of FPGA
cycles until the SNES control signals have been clocked into the shift
registers.

The recently introduced brightness patch partly reacts to this pattern,
momentarily forcing the sd2snes data bus drivers active. Depending on
the SNES CPU's current position in the cycle this could cause a crash,
disrupting the game loading handshake. Upon pushing reset the game would
still run but without long reset or autosave features, so one would
inevitably lose their SRAM contents.

This fix initializes the synchronizers for all active low control
registers with 1's (and the CPU_CLK synchronizer with 0's for good
measure) so the FPGA doesn't make up any accesses that do not exist.
2018-08-07 18:58:00 +02:00
ikari
7d5dd9d2b4 Feature: Brightness limit
This intercepts and overrides writes to $2100, limiting the brightness
written to a configurable value (8..15).
The FPGA feature bitfield is extended to 16 bits to accomodate the 4
additional bits for the brightness limit.
The menu itself does not apply the brightness limit on FPGA level but
"fakes" it by setting the brightness manually. The newly added menu
change hooks are used to reflect the brightness setting as soon as it is
changed during selection.
2018-07-15 00:50:11 +02:00
ikari
bf3e1b0533 Merge branch 'gsu' of https://github.com/RedGuyyyy/sd2snes into RedGuyyyy-gsu 2018-06-05 01:17:06 +02:00
RedGuyyyy
ff85304602 Fixed plot bug in starfox by use non-dithered color to test for transparency. 2018-05-04 21:13:06 -07:00
RedGuyyyy
b70f07a443 Fixed few cycle hole where IRQ and GO bit can make 1->0->1 transition when it should be 1->0. 2018-05-04 19:47:59 -07:00
RedGuyyyy
4d033bf76d Updated timing parameters.
Added support for ingame hooks.  Disabled for Doom.
2018-05-02 07:46:12 -07:00
RedGuyyyy
11dcb3bd59 Fixed timing to improve match with rea carts. Thanks to all the people that contributed.
Fixed 8b multiplies to support 0 cycles of additional latency.
2018-04-22 09:14:48 -07:00
RedGuyyyy
4c970999a7 Added support for second ram chip.
Fixed ram word accesses to do serialized byte transfers.
Cleaned up some code and warnings.
2018-04-21 14:46:36 -07:00
ikari
a8cd32af3d FPGA: experimental brightness patching for 1CHIP systems
This applies a simple rule set to patch CPU writes to the PPU2
brightness register ($2100), avoiding brightness DAC voltage changes
when switching to/from forced blanking, also substituting brightness 0
when the picture is to be darkened momentarily.

This fixes, on 1CHIP consoles:
- darkening of picture along the top edge on Capcom games
- distorted scanlines+garbage on Rudra no Hihou dialogue boxes
- invisible shadow in A.S.P. Air Strike Patrol
2018-04-20 12:02:42 +02:00
RedGuyyyy
5ea8222a91 Fixed ram timing for more ram chips with worse timing by adding additional fpga clock.
Fixed menu config save bug with gsu speed option.
2018-04-15 18:37:21 -07:00
RedGuyyyy
40d1797967 Added gsu speed menu option. 2018-04-15 11:57:34 -07:00
RedGuyyyy
123738d868 Changed ron/ran synchronization to be at next cycle end.
Changed stop to wait on prefetcher.
2018-04-15 06:56:26 -07:00
Maximilian Rehkopf
8e58563955 ExLoROM support (LoROM > 32 Mbits) 2018-04-13 18:00:07 +02:00
RedGuyyyy
c7ef9f5475 Changed save to sd to only operate when it detects a carttype that has saveram.
Fixed sram init bug.
Reverted cache invalidation change.  Looks like it's not the cause of problems.
2018-04-09 18:33:56 -07:00
RedGuyyyy
d87bae698e Added comment about icache flush problem. 2018-04-09 06:50:07 -07:00
RedGuyyyy
3a8177a7a4 Fixed CBR write/cache flush bug.
Fixed potential PBR write bug.
2018-04-08 18:37:01 -07:00
RedGuyyyy
6f177557ae Reverted some of the timing changes for the address enables.
Added full bus access for gsu when it has both ran and ron set.
2018-04-08 14:58:30 -07:00
RedGuyyyy
74280a56af Fixed embarrasing bug introduced by me where stale psram rom data is read rather than the actual header. This fixes a lot.
Added flops for some address module state to improve timing.
Added back periodic saving of cart ram.
2018-04-07 16:32:09 -07:00
RedGuyyyy
4654e9053f Added better CBR write implementation. 2018-04-07 15:00:00 -07:00
RedGuyyyy
ae72262858 Fixed CBR reset bug where SFR write would unconditionally reset it to 0. 2018-04-07 14:07:14 -07:00
RedGuyyyy
9cdcf0e23b Cleaned up address mapping logic.
Cleaned up some commented out dsp and bsx code.
2018-04-07 11:11:40 -07:00
RedGuyyyy
aabcaafbf8 Fixed PBR write to only use 7b of data bus. Voxel demo works with this change. 2018-04-06 21:39:29 -07:00
RedGuyyyy
c403ff92dd Changed DEBUG/MSU/DAC defines to disable debug mode in checkin.
Updated version number.
Fixed FWVER generation bug.
2018-04-04 22:38:44 -07:00
RedGuyyyy
6f975018ef Fixed lack of ROMB and RAMB synchronization with the prefetcher and store buffer, respectively. Fixes doom and maybe other stuff. 2018-04-04 22:03:10 -07:00
RedGuyyyy
36764efa09 Fixed one cycle hole in prefetcher.
Fixed unset save variable in firmware.
2018-04-04 07:27:22 -07:00
RedGuyyyy
a4c5e46634 Added necessary firmware files to load gsu fpga file.
Fixed timing problem in MCU.  In 0.1.7e firmware.
Disabled in-game saving to SD card for gsu games.  Hold reset button to save.
Disabled gsu DEBUG and enabled msu by default.
2018-04-03 06:04:41 -07:00
RedGuyyyy
0965e21f46 Fixed RPIX double op bug. This fixes tunnels in Yoshi's Island. 2018-04-02 19:18:47 -07:00
RedGuyyyy
55c1a2848b Added better bitmap pipeline with write buffering and nonblocking flushes. Seems to introduce a transparency bug. 2018-04-01 17:01:29 -07:00
RedGuyyyy
de405d64f9 Added store buffer. Somehow this fixed Winter Gold...
Fixed DEBUG define to remove the majority of the debugging support.
2018-03-31 20:22:51 -07:00
RedGuyyyy
04a2b8e86e Fixed cache injection addressing bug.
Fixed multiplication timing problems again.  The fix isn't ideal, but this is the only way it worked.
Removed some commented out code as a minor cleanup.
2018-03-31 14:18:15 -07:00
RedGuyyyy
40c9ac9eab Fixed random crash caused by race between PPU IRQ and GO bit being cleared.
Fixed some timing problems.
2018-03-30 19:37:47 -07:00
RedGuyyyy
5c5d511388 Added data prefetcher. 2018-03-30 14:04:52 -07:00
RedGuyyyy
82bb521ce9 Fixed setting of cache valid bits from MMIO write. 2018-03-29 17:12:10 -07:00
RedGuyyyy
08202acaf6 Fixed RPIX condition code generation.
Fixed RPIX/PLOT state bit clears.
2018-03-29 16:26:26 -07:00
RedGuyyyy
de2193ffbf Fixed bug introduced by prior checkin. First 8K is mirrored throughout and not stacked 8K regions. Yoshi's Island starts. 2018-03-29 14:26:28 -07:00
RedGuyyyy
8cd7949d92 Fixed snes->gsu address mapping. Thanks to megari for the changes.
Added reset values for ROMBR and RAMBR.
2018-03-29 07:17:11 -07:00
RedGuyyyy
8aa8efe1ef Fixed bad timing bug with synchronization logic. Enabled L2I cache which now works. 2018-03-28 22:15:00 -07:00