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sd2snes/verilog/sd2snes_dsp
History
ikari 858d660569 Update a slew of Xilinx autogenerated files
2025-06-24 10:58:46 +02:00
..
ipcore_dir
Update a slew of Xilinx autogenerated files
2025-06-24 10:58:46 +02:00
address.v
Give full access to banks C0-FF during in-game hook
2021-07-28 00:51:33 +02:00
cheat.v
comments, wording, cleanup, cosmetics
2021-07-28 02:19:06 +02:00
clk_test.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
config.vh
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
ctx.v
[FPGA/DSP] update save state logic, add source files
2021-07-22 12:16:45 +02:00
dac_buf.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
dac_buf.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
dac.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
dcm.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
dma.v
[FPGA/DSP] update save state logic, add source files
2021-07-22 12:16:45 +02:00
main_assignment_defaults.qdf
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
main_tf.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
main.qsf
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
main.sdc
FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz
2023-02-03 01:37:31 +01:00
main.ucf
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
main.v
comments, wording, cleanup, cosmetics
2021-07-28 02:19:06 +02:00
Makefile
FPGA build: add header files to prerequisites
2021-07-28 01:26:42 +02:00
mcu_cmd.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
msu_databuf.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
msu_databuf.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
msu.v
Ensure MSU-1 data address increment at end of DMA (#208)
2023-03-30 11:09:25 +02:00
pll.ppf
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
pll.qip
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
pll.v
FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz
2023-02-03 01:37:31 +01:00
sd2snes_dsp.qpf
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
sd2snes_dsp.xise
Ensure MSU-1 data address increment at end of DMA (#208)
2023-03-30 11:09:25 +02:00
sd_dma.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
snescmd_buf.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
snescmd_buf.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
spi.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
upd77c25_datram.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
upd77c25_datram.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
upd77c25_datrom.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
upd77c25_datrom.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
upd77c25_pgmrom.qip
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
upd77c25_pgmrom.v
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
upd77c25.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00
updtest_tf.v
FPGA: Move DSPx to separate core
2020-09-24 00:52:50 +02:00