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sd2snes/verilog/sd2snes_obc1/pll.v
ikari fcc1d78923 FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz 
Required to support STM32 clock output (MCO1) which cannot be fed and
prescaled from the CPU clock
2023-02-03 01:37:31 +01:00

15 KiB
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