ikari 858d660569 Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

..

ipcore_dir

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

address.v

FPGA: fix ROM address detection to exclude WRAM

2021-07-28 11:09:49 +02:00

bsx.v

Merge branch 'savestate' of https://github.com/furious/sd2snes into furious-savestate

2019-10-13 02:37:03 +02:00

cheat.v

comments, wording, cleanup, cosmetics

2021-07-28 02:19:06 +02:00

clk_test.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

dac_buf.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

dac_buf.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

dac.v

Revise project structure

2019-05-20 00:33:28 +02:00

dcm.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

dec_table.mif

Revise project structure

2019-05-20 00:33:28 +02:00

dec_table.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

dec_table.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

decoder.py

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

main_assignment_defaults.qdf

Revise project structure

2019-05-20 00:33:28 +02:00

main_tf.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

main.qsf

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

main.sdc

FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz

2023-02-03 01:37:31 +01:00

main.ucf

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

main.v

SA-1 quick fix: increase execution speed (1.10.0 regression)

2023-02-16 08:37:44 +01:00

Makefile

Update global & FPGA makefiles

2020-10-20 23:15:54 +02:00

mcu_cmd.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

msu_databuf.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

msu_databuf.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

msu.v

Ensure MSU-1 data address increment at end of DMA (#208)

2023-03-30 11:09:25 +02:00

optable.txt

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

pll.ppf

Revise project structure

2019-05-20 00:33:28 +02:00

pll.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

pll.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

rtc.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

sa1_div.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1_div.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1_iram.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1_iram.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1_mult.qip

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1_mult.v

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sa1.v

Added CCNT_RESB (wait bit) implementation. Halts SA-1 instruction execute

2023-03-07 22:35:36 +01:00

sd2snes_sa1.qpf

Revise project structure

2019-05-20 00:33:28 +02:00

sd2snes_sa1.xise

Update a slew of Xilinx autogenerated files

2025-06-24 10:58:46 +02:00

sd_dma.v

Added sa1 branch based off of develop.

2018-09-04 08:08:44 -07:00

snescmd_buf.qip

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

snescmd_buf.v

FPGA: Bump Quartus version, update generated files

2021-07-29 23:06:25 +02:00

spi.v

FPGA: misc cleanup

2019-07-05 14:03:05 +02:00