Files
sd2snes/verilog/sd2snes_sa1/Makefile
ikari 6759ce7277 Update global & FPGA makefiles
avoid redundant rebuilding of FPGA cores
2020-10-20 23:15:54 +02:00

15 lines
270 B
Makefile

CORE = sa1
VSRC = address.v cheat.v clk_test.v dac.v dcm.v sa1.v main.v mcu_cmd.v msu.v sd_dma.v spi.v
VHSRC =
COMMON_IP = dec_table sa1_div sa1_iram sa1_mult snescmd_buf
XIL_IP =
XIL_IPCORE_DIR = ipcore_dir
INT_IP = pll
include ../settings.mk
include ../common.mk