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126 lines
3.6 KiB
VHDL
126 lines
3.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: Traducciones Magno
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-- Engineer: Magno
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--
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-- Create Date: 18.03.2018 20:49:09
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-- Design Name:
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-- Module Name: FIFO_Input - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity FIFO_B2B is
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Generic( FIFO_DEPTH : integer := 32;
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PROG_FULL_TH : integer := 16);
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Port( clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din_tready : OUT STD_LOGIC;
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din_tvalid : IN STD_LOGIC;
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din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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dout_tready : IN STD_LOGIC;
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dout_tvalid : OUT STD_LOGIC;
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dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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prog_full : OUT STD_LOGIC );
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end FIFO_B2B;
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architecture Behavioral of FIFO_B2B is
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type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
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signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
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signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
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signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
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signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
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signal din_tready_i : STD_LOGIC := '0';
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signal dout_tvalid_i : STD_LOGIC := '0';
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begin
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Process( clk )
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Begin
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if rising_edge( clk ) then
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if( srst = '1' ) then
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FIFO_Array <= (others => (others => '0'));
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wr_ptr <= 0;
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rd_ptr <= 0;
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data_cnt <= 0;
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else
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-- write command
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if( din_tready_i = '1' AND din_tvalid = '1' ) then
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-- write data to array
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FIFO_Array(wr_ptr) <= din_tdata;
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-- check write pointer limits
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if( wr_ptr = (FIFO_DEPTH-1) ) then
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wr_ptr <= 0;
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else
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wr_ptr <= wr_ptr + 1;
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end if;
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end if;
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-- read command
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if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
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-- check read pointer limits
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if( rd_ptr = (FIFO_DEPTH-1) ) then
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rd_ptr <= 0;
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else
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rd_ptr <= rd_ptr + 1;
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end if;
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end if;
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-- occupancy control
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-- write only
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if((din_tready_i = '1' AND din_tvalid = '1') AND
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(dout_tready = '0' OR dout_tvalid_i = '0')) then
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data_cnt <= data_cnt + 1;
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-- read only
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elsif((din_tready_i = '0' OR din_tvalid = '0') AND
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(dout_tready = '1' AND dout_tvalid_i = '1')) then
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data_cnt <= data_cnt - 1;
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end if;
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end if;
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end if;
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End Process;
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-- first word fall-through
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dout_tdata <= FIFO_Array(rd_ptr);
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dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
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dout_tvalid <= dout_tvalid_i;
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-- flow control signals
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empty <= '1' when data_cnt = 0 else '0';
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full <= NOT din_tready_i;
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prog_full <= '1' when (data_cnt >= PROG_FULL_TH OR srst = '1') else '0';
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din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-1) OR srst = '1') else '1';
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din_tready <= din_tready_i;
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end Behavioral;
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