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sd2snes/verilog/sd2snes_sdd1
History
ikari 858d660569 Update a slew of Xilinx autogenerated files
2025-06-24 10:58:46 +02:00
..
ipcore_dir
Update a slew of Xilinx autogenerated files
2025-06-24 10:58:46 +02:00
address.v
S-DD1: support "mixed mapper" SRAM mapping
2025-06-24 10:56:38 +02:00
cheat.v
comments, wording, cleanup, cosmetics
2021-07-28 02:19:06 +02:00
clk_test.v
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
dac_buf.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
dac_buf.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
dac.v
Revise project structure
2019-05-20 00:33:28 +02:00
DCM_Scope.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
DCM.v
Revise project structure
2019-05-20 00:33:28 +02:00
FIFO_AXIS.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
FIFO_B2B.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
Golomb_0_Decoder.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
Golomb_N_Decoder.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
Input_Manager.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
main.qsf
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
main.sdc
FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz
2023-02-03 01:37:31 +01:00
main.ucf
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
main.v
S-DD1: support "mixed mapper" SRAM mapping
2025-06-24 10:56:38 +02:00
Makefile
Update global & FPGA makefiles
2020-10-20 23:15:54 +02:00
mcu_cmd.v
FPGA: misc cleanup
2019-07-05 14:03:05 +02:00
msu_databuf.qip
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
msu_databuf.v
FPGA: Bump Quartus version, update generated files
2021-07-29 23:06:25 +02:00
msu.v
Ensure MSU-1 data address increment at end of DMA (#208)
2023-03-30 11:09:25 +02:00
Output_Manager.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
pll.ppf
Revise project structure
2019-05-20 00:33:28 +02:00
pll.qip
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
pll.v
FPGA: Change MK3 FPGA clock input from 24MHz to 8MHz
2023-02-03 01:37:31 +01:00
Probability_Estimator.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
sd2snes_sdd1.qpf
Revise project structure
2019-05-20 00:33:28 +02:00
sd2snes_sdd1.xise
Update a slew of Xilinx autogenerated files
2025-06-24 10:58:46 +02:00
sd_dma.v
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
SDD1_Core.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
SDD1.vhd
S-DD1: support "mixed mapper" SRAM mapping
2025-06-24 10:56:38 +02:00
Serializer.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
snescmd_buf.qip
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
snescmd_buf.v
FPGA: General update of generated files
2023-02-03 01:37:32 +01:00
spi.v
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
Test_Main.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00
Test_Top_SDD1.vhd
S-DD1 support by Magno
2019-02-28 18:41:40 +01:00