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61 lines
1.5 KiB
VHDL
61 lines
1.5 KiB
VHDL
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-- Company: Traducciones Magno
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-- Engineer: Magno
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--
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-- Create Date: 20.03.2018 18:42:09
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-- Design Name:
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-- Module Name: Golomb_Decoder - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Golomb_0_Decoder is
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Port( clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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din_tready : OUT STD_LOGIC;
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din_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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din_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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dout_tready : IN STD_LOGIC;
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dout_tdata : OUT STD_LOGIC;
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dout_tlast : OUT STD_LOGIC);
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end Golomb_0_Decoder;
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architecture Behavioral of Golomb_0_Decoder is
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begin
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-- shift by 1 input bitstream each output bit
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din_tready <= dout_tready;
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din_tuser <= "000";
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-- decoded bit is input bit
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dout_tdata <= din_tdata(0);
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-- run length is always one bit
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dout_tlast <= '1';
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end Behavioral;
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