Files
sd2snes/verilog/sd2snes_sdd1/Makefile
ikari 6759ce7277 Update global & FPGA makefiles
avoid redundant rebuilding of FPGA cores
2020-10-20 23:15:54 +02:00

15 lines
411 B
Makefile

CORE = sdd1
VSRC = address.v cheat.v clk_test.v dac.v DCM_Scope.v main.v mcu_cmd.v msu.v sd_dma.v spi.v
VHSRC = FIFO_B2B.vhd FIFO_AXIS.vhd Golomb_0_Decoder.vhd Golomb_N_Decoder.vhd Input_Manager.vhd Output_Manager.vhd Probability_Estimator.vhd SDD1.vhd Serializer.vhd
COMMON_IP = dac_buf msu_databuf snescmd_buf
XIL_IP =
XIL_IPCORE_DIR = ipcore_dir
INT_IP = pll
include ../settings.mk
include ../common.mk