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Fix Minor Maxwell3D Register Ordering Issues
We order all registers in ascending order, a few registers namely `colorLogicOp`, `colorWriteMask`, `clearBuffers` and `depthBiasClamp` were erroneously not following this order which has now been fixed.
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@ -204,18 +204,25 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x5A1, u32> provokingVertexIsLast;
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Register<0x61F, float> depthBiasClamp;
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Register<0x646, u32> cullFaceEnable;
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Register<0x647, type::FrontFace> frontFace;
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Register<0x648, type::CullFace> cullFace;
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Register<0x649, u32> pixelCentreImage;
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Register<0x64B, u32> viewportTransformEnable;
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Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
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struct ColorLogicOp {
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u32 enable;
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type::ColorLogicOp type;
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};
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Register<0x671, ColorLogicOp> colorLogicOp;
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Register<0x674, type::ClearBuffers> clearBuffers;
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Register<0x680, std::array<type::ColorWriteMask, type::RenderTargetCount>> colorWriteMask;
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Register<0x61F, float> depthBiasClamp;
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Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
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struct Semaphore {
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type::Address address; // 0x6C0
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u32 payload; // 0x6C2
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@ -223,12 +230,6 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x6C0, Semaphore> semaphore;
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struct ColorLogicOp {
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u32 enable;
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type::ColorLogicOp type;
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};
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Register<0x671, ColorLogicOp> colorLogicOp;
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struct VertexBuffer {
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union {
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u32 raw;
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