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Fix Minor Maxwell3D Register Ordering Issues

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We order all registers in ascending order, a few registers namely `colorLogicOp`, `colorWriteMask`, `clearBuffers` and `depthBiasClamp` were erroneously not following this order which has now been fixed.
This commit is contained in:
PixelyIon 2021-11-16 15:13:15 +05:30
parent 32de7e5150
commit 476c070c7a
1 changed files with 10 additions and 9 deletions
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19
app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h
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@ -204,18 +204,25 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
Register<0x5A1, u32> provokingVertexIsLast;
Register<0x61F, float> depthBiasClamp;
Register<0x646, u32> cullFaceEnable;
Register<0x647, type::FrontFace> frontFace;
Register<0x648, type::CullFace> cullFace;
Register<0x649, u32> pixelCentreImage;
Register<0x64B, u32> viewportTransformEnable;
Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
struct ColorLogicOp {
u32 enable;
type::ColorLogicOp type;
};
Register<0x671, ColorLogicOp> colorLogicOp;
Register<0x674, type::ClearBuffers> clearBuffers;
Register<0x680, std::array<type::ColorWriteMask, type::RenderTargetCount>> colorWriteMask;
Register<0x61F, float> depthBiasClamp;
Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
struct Semaphore {
type::Address address; // 0x6C0
u32 payload; // 0x6C2
@ -223,12 +230,6 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
};
Register<0x6C0, Semaphore> semaphore;
struct ColorLogicOp {
u32 enable;
type::ColorLogicOp type;
};
Register<0x671, ColorLogicOp> colorLogicOp;
struct VertexBuffer {
union {
u32 raw;