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Fix A2R10G10B10 render target format
This was wrongly described as R10G10B10A2 in the enum when it's actually A2R10G10B10, a format natively supported in Vulkan with just a swizzle.
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@ -208,9 +208,8 @@ namespace skyline::gpu::interconnect {
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FORMAT_NORM_INT_SRGB_CASE(R8G8B8X8, R8G8B8A8);
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FORMAT_NORM_INT_SRGB_CASE(R8G8B8X8, R8G8B8A8);
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FORMAT_SAME_CASE(B8G8R8A8, Unorm);
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FORMAT_SAME_CASE(B8G8R8A8, Unorm);
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FORMAT_SAME_CASE(B8G8R8A8, Srgb);
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FORMAT_SAME_CASE(B8G8R8A8, Srgb);
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/* Not supported by VK
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FORMAT_SAME_CASE(A2R10G10B10, Unorm);
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FORMAT_SAME_CASE(R10G10B10A2, Unorm);
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FORMAT_SAME_CASE(A2R10G10B10, Uint);
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FORMAT_SAME_CASE(R10G10B10A2, Uint);*/
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FORMAT_SAME_INT_CASE(R32G32);
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FORMAT_SAME_INT_CASE(R32G32);
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FORMAT_SAME_CASE(R32G32, Float);
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FORMAT_SAME_CASE(R32G32, Float);
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FORMAT_SAME_CASE(R16G16B16A16, Float);
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FORMAT_SAME_CASE(R16G16B16A16, Float);
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@ -75,6 +75,11 @@ namespace skyline::gpu::format {
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});
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});
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FORMAT_NORM_INT_SRGB(B8G8R8A8, 32, eB8G8R8A8);
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FORMAT_NORM_INT_SRGB(B8G8R8A8, 32, eB8G8R8A8);
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FORMAT_SUFF_NORM_INT(A2B10G10R10, 32, eA2B10G10R10, Pack32);
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FORMAT_SUFF_NORM_INT(A2B10G10R10, 32, eA2B10G10R10, Pack32);
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FORMAT_SUFF_NORM_INT(A2R10G10B10, 32, eA2B10G10R10, Pack32, .swizzle = {
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.blue = swc::Red,
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.red = swc::Blue
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});
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FORMAT_SUFF_NORM_INT_SRGB(A8B8G8R8, 32, eA8B8G8R8, Pack32);
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FORMAT_SUFF_NORM_INT_SRGB(A8B8G8R8, 32, eA8B8G8R8, Pack32);
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FORMAT_INT_FLOAT(R32G32, 32 * 2, eR32G32);
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FORMAT_INT_FLOAT(R32G32, 32 * 2, eR32G32);
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FORMAT_NORM_INT_FLOAT(R16G16B16A16, 16 * 4, eR16G16B16A16);
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FORMAT_NORM_INT_FLOAT(R16G16B16A16, 16 * 4, eR16G16B16A16);
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@ -86,8 +86,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
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R16G16B16X16Float = 0xCE,
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R16G16B16X16Float = 0xCE,
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B8G8R8A8Unorm = 0xCF,
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B8G8R8A8Unorm = 0xCF,
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B8G8R8A8Srgb = 0xD0,
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B8G8R8A8Srgb = 0xD0,
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R10G10B10A2Unorm = 0xD1,
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A2R10G10B10Unorm = 0xD1,
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R10G10B10A2Uint = 0xD2,
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A2R10G10B10Uint = 0xD2,
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R8G8B8A8Unorm = 0xD5,
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R8G8B8A8Unorm = 0xD5,
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R8G8B8A8Srgb = 0xD6,
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R8G8B8A8Srgb = 0xD6,
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R8G8B8X8Snorm = 0xD7,
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R8G8B8X8Snorm = 0xD7,
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