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Add support for 1D remapped buffer clears

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TheASVigilante 2023-02-19 15:19:02 +01:00 committed by Billy Laws
parent 4c3fed6cd0
commit 70ee36e85c
3 changed files with 40 additions and 0 deletions
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28
app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.cpp
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@ -52,4 +52,32 @@ namespace skyline::gpu::interconnect {
});
});
}
void MaxwellDma::Clear(span<u8> mapping, u32 value) {
if (!util::IsAligned(mapping.size(), 4))
throw exception("Cleared buffer's size is not aligned to 4 bytes!");
auto clearBuf{gpu.buffer.FindOrCreate(mapping, executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
executor.AttachLockedBuffer(buffer, std::move(lock));
})};
executor.AttachBuffer(clearBuf);
clearBuf.GetBuffer()->BlockSequencedCpuBackingWrites();
clearBuf.GetBuffer()->MarkGpuDirty();
executor.AddOutsideRpCommand([clearBuf, value](vk::raii::CommandBuffer &commandBuffer, const std::shared_ptr<FenceCycle> &, GPU &gpu) {
commandBuffer.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands, vk::PipelineStageFlagBits::eTransfer, {}, vk::MemoryBarrier{
.srcAccessMask = vk::AccessFlagBits::eMemoryRead,
.dstAccessMask = vk::AccessFlagBits::eTransferRead | vk::AccessFlagBits::eTransferWrite
}, {}, {});
auto clearBufBinding{clearBuf.GetBinding(gpu)};
commandBuffer.fillBuffer(clearBufBinding.buffer, clearBufBinding.offset, clearBufBinding.size, value);
commandBuffer.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, vk::PipelineStageFlagBits::eAllCommands, {}, vk::MemoryBarrier{
.srcAccessMask = vk::AccessFlagBits::eTransferWrite,
.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
}, {}, {});
});
}
}

2
app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.h
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@ -30,5 +30,7 @@ namespace skyline::gpu::interconnect {
MaxwellDma(GPU &gpu, soc::gm20b::ChannelContext &channelCtx);
void Copy(span<u8> dstMapping, span<u8> srcMapping);
void Clear(span<u8> mapping, u32 value);
};
}

10
app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_dma.cpp
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@ -89,7 +89,17 @@ namespace skyline::soc::gm20b::engine {
auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, *registers.lineLengthIn * dstBpp)};
if (registers.launchDma->remapEnable) [[unlikely]] {
// Remapped buffer clears
if ((registers.remapComponents->dstX == Registers::RemapComponents::Swizzle::ConstA) &&
(registers.remapComponents->dstY == Registers::RemapComponents::Swizzle::ConstA) &&
(registers.remapComponents->dstZ == Registers::RemapComponents::Swizzle::ConstA) &&
(registers.remapComponents->dstW == Registers::RemapComponents::Swizzle::ConstA) &&
(registers.remapComponents->ComponentSize() == 4)) {
for (size_t currMapping{dstMappings.size()}; currMapping; --currMapping)
interconnect.Clear(dstMappings[currMapping], *registers.remapConstA);
} else {
Logger::Warn("Remapped DMA copies are unimplemented!");
}
} else {
if (srcMappings.size() != 1 || dstMappings.size() != 1) [[unlikely]]
channelCtx.asCtx->gmmu.Copy(u64{*registers.offsetOut}, u64{*registers.offsetIn}, *registers.lineLengthIn);