mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-11-27 01:44:15 +01:00
Implement accelerated uploads/copies through buffer manager
Previously, both I2M uploads and DMA copies would force GPU serialisation if they happened to hit a trap or were used to copy GPU dirty buffers. By using the buffer manager to implement them on the host GPU we can avoid such slowdowns entiely.
This commit is contained in:
parent
c5ec484d9a
commit
cac287d9fd
@ -186,6 +186,8 @@ add_library(skyline SHARED
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${source_DIR}/skyline/gpu/cache/renderpass_cache.cpp
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${source_DIR}/skyline/gpu/cache/renderpass_cache.cpp
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${source_DIR}/skyline/gpu/cache/framebuffer_cache.cpp
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${source_DIR}/skyline/gpu/cache/framebuffer_cache.cpp
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${source_DIR}/skyline/gpu/interconnect/fermi_2d.cpp
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${source_DIR}/skyline/gpu/interconnect/fermi_2d.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_dma.cpp
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${source_DIR}/skyline/gpu/interconnect/inline2memory.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/common.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/common.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/active_state.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/active_state.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/pipeline_state.cpp
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${source_DIR}/skyline/gpu/interconnect/maxwell_3d/pipeline_state.cpp
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50
app/src/main/cpp/skyline/gpu/interconnect/inline2memory.cpp
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50
app/src/main/cpp/skyline/gpu/interconnect/inline2memory.cpp
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@ -0,0 +1,50 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/ryujinx/)
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <gpu/buffer_manager.h>
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#include <soc/gm20b/gmmu.h>
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#include <soc/gm20b/channel.h>
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#include "inline2memory.h"
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namespace skyline::gpu::interconnect {
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using IOVA = soc::gm20b::IOVA;
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Inline2Memory::Inline2Memory(GPU &gpu, soc::gm20b::ChannelContext &channelCtx)
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: gpu{gpu},
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channelCtx{channelCtx},
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executor{channelCtx.executor} {}
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void Inline2Memory::Upload(IOVA dst, span<u32> src) {
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(dst, src.size_bytes())};
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if (dstMappings.size() > 1)
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Logger::Warn("Split mapping are unsupported for DMA copies");
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auto dstBuf{gpu.buffer.FindOrCreate(dstMappings.front(), executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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executor.AttachLockedBuffer(buffer, std::move(lock));
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})};
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ContextLock dstBufLock{executor.tag, dstBuf};
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dstBuf.Write(src.cast<u8>(), 0, [&]() {
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executor.AttachLockedBufferView(dstBuf, std::move(dstBufLock));
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// This will prevent any CPU accesses to backing for the duration of the usage
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dstBuf.GetBuffer()->BlockAllCpuBackingWrites();
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auto srcGpuAllocation{gpu.megaBufferAllocator.Push(executor.cycle, src.cast<u8>())};
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executor.AddOutsideRpCommand([srcGpuAllocation, dstBuf, src](vk::raii::CommandBuffer &commandBuffer, const std::shared_ptr<FenceCycle> &, GPU &) {
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vk::BufferCopy copyRegion{
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.size = src.size_bytes(),
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.srcOffset = srcGpuAllocation.offset,
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.dstOffset = dstBuf.GetOffset()
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};
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commandBuffer.copyBuffer(srcGpuAllocation.buffer, dstBuf.GetBuffer()->GetBacking(), copyRegion);
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commandBuffer.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, vk::PipelineStageFlagBits::eAllCommands, {}, vk::MemoryBarrier{
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.srcAccessMask = vk::AccessFlagBits::eTransferWrite,
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.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite
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}, {}, {});
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});
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});
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}
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}
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36
app/src/main/cpp/skyline/gpu/interconnect/inline2memory.h
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36
app/src/main/cpp/skyline/gpu/interconnect/inline2memory.h
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@ -0,0 +1,36 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/ryujinx/)
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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#include <soc/gm20b/gmmu.h>
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namespace skyline::gpu {
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class GPU;
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}
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namespace skyline::soc::gm20b {
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struct ChannelContext;
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}
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namespace skyline::gpu::interconnect {
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class CommandExecutor;
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/**
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* @brief Handles translating I2M operations to Vulkan
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*/
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class Inline2Memory {
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private:
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using IOVA = soc::gm20b::IOVA;
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GPU &gpu;
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soc::gm20b::ChannelContext &channelCtx;
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gpu::interconnect::CommandExecutor &executor;
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public:
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Inline2Memory(GPU &gpu, soc::gm20b::ChannelContext &channelCtx);
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void Upload(IOVA dst, span<u32> src);
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};
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}
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61
app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.cpp
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app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.cpp
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@ -0,0 +1,61 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/ryujinx/)
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <gpu/buffer_manager.h>
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#include <soc/gm20b/gmmu.h>
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#include <soc/gm20b/channel.h>
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#include "maxwell_dma.h"
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namespace skyline::gpu::interconnect {
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using IOVA = soc::gm20b::IOVA;
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MaxwellDma::MaxwellDma(GPU &gpu, soc::gm20b::ChannelContext &channelCtx)
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: gpu{gpu},
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channelCtx{channelCtx},
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executor{channelCtx.executor} {}
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void MaxwellDma::Copy(IOVA dst, IOVA src, size_t size) {
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(src, size)};
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(dst, size)};
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if (srcMappings.size() > 1 || dstMappings.size() > 1)
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Logger::Warn("Split mapping are unsupported for DMA copies");
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auto srcBuf{gpu.buffer.FindOrCreate(srcMappings.front(), executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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executor.AttachLockedBuffer(buffer, std::move(lock));
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})};
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ContextLock srcBufLock{executor.tag, srcBuf};
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auto dstBuf{gpu.buffer.FindOrCreate(dstMappings.front(), executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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executor.AttachLockedBuffer(buffer, std::move(lock));
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})};
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ContextLock dstBufLock{executor.tag, dstBuf};
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dstBuf.CopyFrom(srcBuf, [&]() {
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executor.AttachLockedBufferView(srcBuf, std::move(srcBufLock));
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executor.AttachLockedBufferView(dstBuf, std::move(dstBufLock));
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// This will prevent any CPU accesses to backing for the duration of the usage
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// GPU dirtiness will be handled on the CopyFrom end as it's not always necessary
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srcBuf.GetBuffer()->BlockAllCpuBackingWrites();
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dstBuf.GetBuffer()->BlockAllCpuBackingWrites();
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executor.AddOutsideRpCommand([srcBuf, dstBuf](vk::raii::CommandBuffer &commandBuffer, const std::shared_ptr<FenceCycle> &, GPU &) {
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commandBuffer.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands, vk::PipelineStageFlagBits::eTransfer, {}, vk::MemoryBarrier{
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.srcAccessMask = vk::AccessFlagBits::eMemoryRead,
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.dstAccessMask = vk::AccessFlagBits::eTransferRead | vk::AccessFlagBits::eTransferWrite
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}, {}, {});
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vk::BufferCopy copyRegion{
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.size = srcBuf.size,
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.srcOffset = srcBuf.GetOffset(),
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.dstOffset = dstBuf.GetOffset()
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};
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commandBuffer.copyBuffer(srcBuf.GetBuffer()->GetBacking(), dstBuf.GetBuffer()->GetBacking(), copyRegion);
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commandBuffer.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, vk::PipelineStageFlagBits::eAllCommands, {}, vk::MemoryBarrier{
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.srcAccessMask = vk::AccessFlagBits::eTransferWrite,
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.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
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}, {}, {});
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});
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});
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}
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}
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36
app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.h
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36
app/src/main/cpp/skyline/gpu/interconnect/maxwell_dma.h
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@ -0,0 +1,36 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/ryujinx/)
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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#include <soc/gm20b/gmmu.h>
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namespace skyline::gpu {
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class GPU;
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}
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namespace skyline::soc::gm20b {
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struct ChannelContext;
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}
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namespace skyline::gpu::interconnect {
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class CommandExecutor;
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/**
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* @brief Handles translating Maxwell DMA operations to Vulkan
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*/
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class MaxwellDma {
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private:
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using IOVA = soc::gm20b::IOVA;
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GPU &gpu;
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soc::gm20b::ChannelContext &channelCtx;
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gpu::interconnect::CommandExecutor &executor;
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public:
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MaxwellDma(GPU &gpu, soc::gm20b::ChannelContext &channelCtx);
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void Copy(IOVA dst, IOVA src, size_t size);
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};
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}
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#include "inline2memory.h"
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#include "inline2memory.h"
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namespace skyline::soc::gm20b::engine {
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namespace skyline::soc::gm20b::engine {
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Inline2MemoryBackend::Inline2MemoryBackend(ChannelContext &channelCtx) : channelCtx(channelCtx) {}
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Inline2MemoryBackend::Inline2MemoryBackend(const DeviceState &state, ChannelContext &channelCtx)
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: interconnect{*state.gpu, channelCtx},
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channelCtx{channelCtx} {}
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void Inline2MemoryBackend::LaunchDma(Inline2MemoryBackend::RegisterState &state) {
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void Inline2MemoryBackend::LaunchDma(Inline2MemoryBackend::RegisterState &state) {
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writeOffset = 0;
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writeOffset = 0;
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if (state.launchDma.completion == RegisterState::DmaCompletionType::ReleaseSemaphore)
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if (state.launchDma.completion == RegisterState::DmaCompletionType::ReleaseSemaphore)
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throw exception("Semaphore release on I2M completion is not supported!");
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throw exception("Semaphore release on I2M completion is not supported!");
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channelCtx.executor.Submit();
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if (state.launchDma.layout == RegisterState::DmaDstMemoryLayout::Pitch && state.lineCount == 1) {
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if (state.launchDma.layout == RegisterState::DmaDstMemoryLayout::Pitch && state.lineCount == 1) {
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// TODO: we can do this with the buffer manager to avoid some overhead in the future
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Logger::Debug("range: 0x{:X} -> 0x{:X}", u64{state.offsetOut}, u64{state.offsetOut} + buffer.size() * 0x4);
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Logger::Debug("range: 0x{:X} -> 0x{:X}", u64{state.offsetOut}, u64{state.offsetOut} + buffer.size() * 0x4);
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channelCtx.asCtx->gmmu.Write(state.offsetOut, span(buffer));
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interconnect.Upload(u64{state.offsetOut}, span{buffer});
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} else {
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} else {
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channelCtx.executor.Submit();
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Logger::Warn("Non-linear I2M uploads are not supported!");
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Logger::Warn("Non-linear I2M uploads are not supported!");
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}
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}
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}
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}
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@ -49,7 +49,7 @@ namespace skyline::soc::gm20b::engine {
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CompleteDma(state);
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CompleteDma(state);
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}
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}
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Inline2Memory::Inline2Memory(ChannelContext &channelCtx) : backend(channelCtx) {}
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Inline2Memory::Inline2Memory(const DeviceState &state, ChannelContext &channelCtx) : backend{state, channelCtx} {}
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__attribute__((always_inline)) void Inline2Memory::CallMethod(u32 method, u32 argument) {
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__attribute__((always_inline)) void Inline2Memory::CallMethod(u32 method, u32 argument) {
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Logger::Verbose("Called method in I2M: 0x{:X} args: 0x{:X}", method, argument);
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Logger::Verbose("Called method in I2M: 0x{:X} args: 0x{:X}", method, argument);
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#pragma once
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#pragma once
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#include <common.h>
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#include <common.h>
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#include <gpu/interconnect/inline2memory.h>
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#include "engine.h"
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#include "engine.h"
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namespace skyline::soc::gm20b {
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namespace skyline::soc::gm20b {
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@ -18,6 +19,7 @@ namespace skyline::soc::gm20b::engine {
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private:
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private:
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std::vector<u32> buffer; //!< Temporary buffer to hold data being currently uploaded
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std::vector<u32> buffer; //!< Temporary buffer to hold data being currently uploaded
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u32 writeOffset{}; //!< Current write offset in words into `buffer`
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u32 writeOffset{}; //!< Current write offset in words into `buffer`
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gpu::interconnect::Inline2Memory interconnect;
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ChannelContext &channelCtx;
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ChannelContext &channelCtx;
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public:
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public:
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@ -124,7 +126,7 @@ namespace skyline::soc::gm20b::engine {
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void CompleteDma(RegisterState &state);
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void CompleteDma(RegisterState &state);
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public:
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public:
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Inline2MemoryBackend(ChannelContext &channelCtx);
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Inline2MemoryBackend(const DeviceState &state, ChannelContext &channelCtx);
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/**
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/**
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* @brief Should be called when launchDma in `state` is written to
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* @brief Should be called when launchDma in `state` is written to
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@ -164,7 +166,7 @@ namespace skyline::soc::gm20b::engine {
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} registers{};
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} registers{};
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public:
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public:
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Inline2Memory(ChannelContext &channelCtx);
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Inline2Memory(const DeviceState &state, ChannelContext &channelCtx);
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void CallMethod(u32 method, u32 argument);
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void CallMethod(u32 method, u32 argument);
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namespace skyline::soc::gm20b::engine {
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namespace skyline::soc::gm20b::engine {
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KeplerCompute::KeplerCompute(const DeviceState &state, ChannelContext &channelCtx)
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KeplerCompute::KeplerCompute(const DeviceState &state, ChannelContext &channelCtx)
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: syncpoints(state.soc->host1x.syncpoints), i2m(channelCtx) {}
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: syncpoints{state.soc->host1x.syncpoints}, i2m{state, channelCtx} {}
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__attribute__((always_inline)) void KeplerCompute::CallMethod(u32 method, u32 argument) {
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__attribute__((always_inline)) void KeplerCompute::CallMethod(u32 method, u32 argument) {
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Logger::Verbose("Called method in Kepler compute: 0x{:X} args: 0x{:X}", method, argument);
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Logger::Verbose("Called method in Kepler compute: 0x{:X} args: 0x{:X}", method, argument);
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#include "maxwell_dma.h"
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#include "maxwell_dma.h"
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namespace skyline::soc::gm20b::engine {
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namespace skyline::soc::gm20b::engine {
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MaxwellDma::MaxwellDma(const DeviceState &state, ChannelContext &channelCtx, gpu::interconnect::CommandExecutor &executor)
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MaxwellDma::MaxwellDma(const DeviceState &state, ChannelContext &channelCtx)
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: channelCtx(channelCtx), syncpoints(state.soc->host1x.syncpoints), executor(executor) {}
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: channelCtx{channelCtx},
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syncpoints{state.soc->host1x.syncpoints},
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interconnect{*state.gpu, channelCtx} {}
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__attribute__((always_inline)) void MaxwellDma::CallMethod(u32 method, u32 argument) {
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__attribute__((always_inline)) void MaxwellDma::CallMethod(u32 method, u32 argument) {
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Logger::Verbose("Called method in Maxwell DMA: 0x{:X} args: 0x{:X}", method, argument);
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Logger::Verbose("Called method in Maxwell DMA: 0x{:X} args: 0x{:X}", method, argument);
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@ -36,8 +38,8 @@ namespace skyline::soc::gm20b::engine {
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return;
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return;
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}
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}
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executor.Submit();
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if (registers.launchDma->multiLineEnable) {
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if (registers.launchDma->multiLineEnable) {
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channelCtx.executor.Submit();
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if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::Pitch &&
|
if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::Pitch &&
|
||||||
registers.launchDma->dstMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear)
|
registers.launchDma->dstMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear)
|
||||||
CopyPitchToBlockLinear();
|
CopyPitchToBlockLinear();
|
||||||
@ -51,7 +53,7 @@ namespace skyline::soc::gm20b::engine {
|
|||||||
// 1D buffer copy
|
// 1D buffer copy
|
||||||
// TODO: implement swizzled 1D copies based on VMM 'kind'
|
// TODO: implement swizzled 1D copies based on VMM 'kind'
|
||||||
Logger::Debug("src: 0x{:X} dst: 0x{:X} size: 0x{:X}", u64{*registers.offsetIn}, u64{*registers.offsetOut}, *registers.lineLengthIn);
|
Logger::Debug("src: 0x{:X} dst: 0x{:X} size: 0x{:X}", u64{*registers.offsetIn}, u64{*registers.offsetOut}, *registers.lineLengthIn);
|
||||||
channelCtx.asCtx->gmmu.Copy(*registers.offsetOut, *registers.offsetIn, *registers.lineLengthIn);
|
interconnect.Copy(u64{*registers.offsetOut}, u64{*registers.offsetIn}, u64{*registers.lineLengthIn});
|
||||||
}
|
}
|
||||||
|
|
||||||
ReleaseSemaphore();
|
ReleaseSemaphore();
|
||||||
|
@ -3,6 +3,7 @@
|
|||||||
|
|
||||||
#pragma once
|
#pragma once
|
||||||
|
|
||||||
|
#include <gpu/interconnect/maxwell_dma.h>
|
||||||
#include "engine.h"
|
#include "engine.h"
|
||||||
|
|
||||||
namespace skyline::gpu::interconnect {
|
namespace skyline::gpu::interconnect {
|
||||||
@ -21,7 +22,7 @@ namespace skyline::soc::gm20b::engine {
|
|||||||
private:
|
private:
|
||||||
host1x::SyncpointSet &syncpoints;
|
host1x::SyncpointSet &syncpoints;
|
||||||
ChannelContext &channelCtx;
|
ChannelContext &channelCtx;
|
||||||
gpu::interconnect::CommandExecutor &executor;
|
gpu::interconnect::MaxwellDma interconnect;
|
||||||
|
|
||||||
void HandleMethod(u32 method, u32 argument);
|
void HandleMethod(u32 method, u32 argument);
|
||||||
|
|
||||||
@ -253,7 +254,7 @@ namespace skyline::soc::gm20b::engine {
|
|||||||
static_assert(sizeof(Registers) == (EngineMethodsEnd * 0x4));
|
static_assert(sizeof(Registers) == (EngineMethodsEnd * 0x4));
|
||||||
#pragma pack(pop)
|
#pragma pack(pop)
|
||||||
|
|
||||||
MaxwellDma(const DeviceState &state, ChannelContext &channelCtx, gpu::interconnect::CommandExecutor &executor);
|
MaxwellDma(const DeviceState &state, ChannelContext &channelCtx);
|
||||||
|
|
||||||
void CallMethod(u32 method, u32 argument);
|
void CallMethod(u32 method, u32 argument);
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user