mirror of
https://github.com/dborth/snes9xgx.git
synced 2024-11-24 11:39:21 +01:00
adf61aef32
- Fixed invalid memory accesses in C4 and OBC1. MMX3 Toxic Seahorse stage now can be emulated with HDMA. (zones) - Updated snapshot to prevent desync. Added some variables related to APU and HDMA. (gocha)
570 lines
15 KiB
C++
570 lines
15 KiB
C++
/**********************************************************************************
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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(c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com),
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Jerremy Koot (jkoot@snes9x.com)
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(c) Copyright 2002 - 2004 Matthew Kendora
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(c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org)
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(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
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(c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net)
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(c) Copyright 2002 - 2006 funkyass (funkyass@spam.shaw.ca),
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Kris Bleakley (codeviolation@hotmail.com)
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(c) Copyright 2002 - 2007 Brad Jorsch (anomie@users.sourceforge.net),
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Nach (n-a-c-h@users.sourceforge.net),
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zones (kasumitokoduck@yahoo.com)
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(c) Copyright 2006 - 2007 nitsuja
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BS-X C emulator code
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(c) Copyright 2005 - 2006 Dreamer Nom,
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zones
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C4 x86 assembler and some C emulation code
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(c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com),
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Nach,
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zsKnight (zsknight@zsnes.com)
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C4 C++ code
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(c) Copyright 2003 - 2006 Brad Jorsch,
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Nach
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DSP-1 emulator code
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(c) Copyright 1998 - 2006 _Demo_,
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Andreas Naive (andreasnaive@gmail.com)
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Gary Henderson,
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Ivar (ivar@snes9x.com),
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John Weidman,
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Kris Bleakley,
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Matthew Kendora,
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Nach,
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neviksti (neviksti@hotmail.com)
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DSP-2 emulator code
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(c) Copyright 2003 John Weidman,
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Kris Bleakley,
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Lord Nightmare (lord_nightmare@users.sourceforge.net),
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Matthew Kendora,
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neviksti
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DSP-3 emulator code
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(c) Copyright 2003 - 2006 John Weidman,
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Kris Bleakley,
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Lancer,
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z80 gaiden
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DSP-4 emulator code
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(c) Copyright 2004 - 2006 Dreamer Nom,
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John Weidman,
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Kris Bleakley,
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Nach,
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z80 gaiden
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OBC1 emulator code
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(c) Copyright 2001 - 2004 zsKnight,
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pagefault (pagefault@zsnes.com),
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Kris Bleakley,
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Ported from x86 assembler to C by sanmaiwashi
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SPC7110 and RTC C++ emulator code
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(c) Copyright 2002 Matthew Kendora with research by
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zsKnight,
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John Weidman,
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Dark Force
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S-DD1 C emulator code
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(c) Copyright 2003 Brad Jorsch with research by
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Andreas Naive,
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John Weidman
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S-RTC C emulator code
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(c) Copyright 2001-2006 byuu,
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John Weidman
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ST010 C++ emulator code
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(c) Copyright 2003 Feather,
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John Weidman,
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Kris Bleakley,
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Matthew Kendora
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Super FX x86 assembler emulator code
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(c) Copyright 1998 - 2003 _Demo_,
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pagefault,
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zsKnight,
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Super FX C emulator code
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(c) Copyright 1997 - 1999 Ivar,
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Gary Henderson,
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John Weidman
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Sound DSP emulator code is derived from SNEeSe and OpenSPC:
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(c) Copyright 1998 - 2003 Brad Martin
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(c) Copyright 1998 - 2006 Charles Bilyue'
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SH assembler code partly based on x86 assembler code
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(c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se)
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2xSaI filter
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(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
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HQ2x, HQ3x, HQ4x filters
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(c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com)
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Win32 GUI code
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(c) Copyright 2003 - 2006 blip,
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funkyass,
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Matthew Kendora,
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Nach,
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nitsuja
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Mac OS GUI code
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(c) Copyright 1998 - 2001 John Stiles
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(c) Copyright 2001 - 2007 zones
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Specific ports contains the works of other authors. See headers in
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individual files.
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Snes9x homepage: http://www.snes9x.com
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Permission to use, copy, modify and/or distribute Snes9x in both binary
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and source form, for non-commercial purposes, is hereby granted without
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fee, providing that this license information and copyright notice appear
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with all copies and any derived work.
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This software is provided 'as-is', without any express or implied
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warranty. In no event shall the authors be held liable for any damages
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arising from the use of this software or it's derivatives.
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Snes9x is freeware for PERSONAL USE only. Commercial users should
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seek permission of the copyright holders first. Commercial use includes,
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but is not limited to, charging money for Snes9x or software derived from
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Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
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using Snes9x as a promotion for your commercial product.
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The copyright holders request that bug fixes and improvements to the code
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should be forwarded to them so everyone can benefit from the modifications
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in future versions.
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Super NES and Super Nintendo Entertainment System are trademarks of
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Nintendo Co., Limited and its subsidiary companies.
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**********************************************************************************/
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#include "snes9x.h"
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#include "memmap.h"
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#include "cpuops.h"
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#include "ppu.h"
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#include "cpuexec.h"
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#include "debug.h"
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#include "snapshot.h"
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#include "gfx.h"
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#include "missing.h"
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#include "apu.h"
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#include "dma.h"
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#include "sa1.h"
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#include "spc7110.h"
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#ifndef ZSNES_FX
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#include "fxemu.h"
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extern struct FxInit_s SuperFX;
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#endif
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void S9xMainLoop (void)
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{
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if(ICPU.SavedAtOp)
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{
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ICPU.SavedAtOp = FALSE;
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Registers.PCw = CPU.PBPCAtOpcodeStart;
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if(CPU.PCBase)
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CPU.Cycles -= CPU.MemSpeed;
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goto doOp;
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}
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for (;;)
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{
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if (CPU.Flags)
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{
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if (CPU.Flags & NMI_FLAG)
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{
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if (Timings.NMITriggerPos <= CPU.Cycles)
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{
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CPU.Flags &= ~NMI_FLAG;
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Timings.NMITriggerPos = 0xffff;
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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}
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S9xOpcode_NMI();
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}
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}
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#ifdef DEBUGGER
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if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
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{
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for (int Break = 0; Break != 6; Break++)
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{
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if (S9xBreakpoint[Break].Enabled &&
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S9xBreakpoint[Break].Bank == Registers.PB &&
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S9xBreakpoint[Break].Address == Registers.PCw)
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{
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if (S9xBreakpoint[Break].Enabled == 2)
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S9xBreakpoint[Break].Enabled = TRUE;
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else
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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}
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}
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#endif
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CHECK_SOUND();
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if (CPU.Flags & IRQ_FLAG)
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{
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if (CPU.IRQPending)
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// FIXME: In case of IRQ during WRAM refresh
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CPU.IRQPending = 0;
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else
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{
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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}
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if (CPU.IRQActive && !Settings.DisableIRQ)
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{
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if (!CheckFlag(IRQ))
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// in IRQ handler $4211 is supposed to be read, so IRQ_FLAG should be cleared.
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S9xOpcode_IRQ();
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}
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else
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CPU.Flags &= ~IRQ_FLAG;
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}
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}
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if (CPU.Flags & SCAN_KEYS_FLAG)
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break;
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#ifdef DEBUGGER
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if (CPU.Flags & DEBUG_MODE_FLAG)
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break;
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if (CPU.Flags & TRACE_FLAG)
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S9xTrace();
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if (CPU.Flags & SINGLE_STEP_FLAG)
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{
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CPU.Flags &= ~SINGLE_STEP_FLAG;
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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#endif
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}
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#ifdef CPU_SHUTDOWN
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CPU.PBPCAtOpcodeStart = Registers.PBPC;
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#endif
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doOp:
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register uint8 Op;
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register struct SOpcodes *Opcodes;
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CPU.PrevCycles = CPU.Cycles;
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if (CPU.PCBase)
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{
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Op = CPU.PCBase[Registers.PCw];
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CPU.Cycles += CPU.MemSpeed;
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Opcodes = ICPU.S9xOpcodes;
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}
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else
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{
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Op = S9xGetByte(Registers.PBPC);
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OpenBus = Op;
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Opcodes = S9xOpcodesSlow;
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}
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if ((Registers.PCw&MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
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{
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uint8 *oldPCBase = CPU.PCBase;
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CPU.PCBase = GetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
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if (oldPCBase!=CPU.PCBase || (Registers.PCw&~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
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Opcodes = S9xOpcodesSlow;
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}
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Registers.PCw++;
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(*Opcodes[Op].S9xOpcode)();
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if(ICPU.SavedAtOp)
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{
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ICPU.SavedAtOp = false;
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continue;
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}
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S9xAPUExecute();
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if (SA1.Executing)
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S9xSA1MainLoop();
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while (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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}
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S9xPackStatus();
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APURegisters.PC = IAPU.PC - IAPU.RAM;
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S9xAPUPackStatus();
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if (CPU.Flags & SCAN_KEYS_FLAG)
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{
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#ifdef DEBUGGER
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if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
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#endif
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S9xSyncSpeed();
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CPU.Flags &= ~SCAN_KEYS_FLAG;
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}
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}
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void S9xSetIRQ (uint32 source)
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{
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CPU.IRQActive |= source;
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CPU.Flags |= IRQ_FLAG;
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if (CPU.WaitingForInterrupt)
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{
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// Force IRQ to trigger immediately after WAI -
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// Final Fantasy Mystic Quest crashes without this.
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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}
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}
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void S9xClearIRQ (uint32 source)
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{
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CLEAR_IRQ_SOURCE(source);
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}
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void S9xDoHEventProcessing (void)
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{
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#ifdef DEBUGGER
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char mes[256];
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#endif
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#ifdef CPU_SHUTDOWN
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CPU.WaitCounter++;
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#endif
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switch (CPU.WhichEvent)
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{
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case HC_HBLANK_START_EVENT:
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S9xCheckMissingHTimerPosition(Timings.HBlankStart);
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break;
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case HC_HDMA_START_EVENT:
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if (PPU.HDMA && CPU.V_Counter <= PPU.ScreenHeight)
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{
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#ifdef DEBUGGER
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sprintf(mes, "*** HDMA HC:%04d, Channel:%02x", CPU.Cycles, PPU.HDMA);
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S9xTraceMessage(mes);
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#endif
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PPU.HDMA = S9xDoHDMA(PPU.HDMA);
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}
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S9xCheckMissingHTimerPosition(Timings.HDMAStart);
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break;
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case HC_HCOUNTER_MAX_EVENT:
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#ifndef ZSNES_FX
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if (Settings.SuperFX)
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{
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if (!SuperFX.oneLineDone)
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S9xSuperFXExec();
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SuperFX.oneLineDone = FALSE;
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}
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#else
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S9xSuperFXExec();
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#endif
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#ifndef STORM
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if (Settings.SoundSync)
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S9xGenerateSound();
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#endif
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CPU.Cycles -= Timings.H_Max;
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APU.NextAPUTimerPos -= (Timings.H_Max << SNES_APU_ACCURACY);
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APU.Cycles -= (Timings.H_Max << SNES_APU_ACCURACY);
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if ((Timings.NMITriggerPos != 0xffff) && (Timings.NMITriggerPos >= Timings.H_Max))
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Timings.NMITriggerPos -= Timings.H_Max;
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ICPU.Scanline++;
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CPU.V_Counter++;
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if (CPU.V_Counter >= Timings.V_Max) // V ranges from 0 to Timings.V_Max - 1
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{
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CPU.V_Counter = 0;
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Timings.InterlaceField ^= 1;
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// From byuu:
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// [NTSC]
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// interlace mode has 525 scanlines: 263 on the even frame, and 262 on the odd.
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// non-interlace mode has 524 scanlines: 262 scanlines on both even and odd frames.
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// [PAL] <PAL info is unverified on hardware>
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// interlace mode has 625 scanlines: 313 on the even frame, and 312 on the odd.
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// non-interlace mode has 624 scanlines: 312 scanlines on both even and odd frames.
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if (IPPU.Interlace && !Timings.InterlaceField)
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Timings.V_Max = Timings.V_Max_Master + 1; // 263 (NTSC), 313?(PAL)
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else
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Timings.V_Max = Timings.V_Max_Master; // 262 (NTSC), 312?(PAL)
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Memory.FillRAM[0x213F] ^= 0x80;
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PPU.RangeTimeOver = 0;
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// FIXME: reading $4210 will wait 2 cycles, then perform reading, then wait 4 more cycles.
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Memory.FillRAM[0x4210] = Model->_5A22;
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CPU.Flags &= ~NMI_FLAG;
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Timings.NMITriggerPos = 0xffff;
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ICPU.Frame++;
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PPU.HVBeamCounterLatched = 0;
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CPU.Flags |= SCAN_KEYS_FLAG;
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}
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// From byuu:
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// In non-interlace mode, there are 341 dots per scanline, and 262 scanlines per frame.
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// On odd frames, scanline 240 is one dot short.
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// In interlace mode, there are always 341 dots per scanline. Even frames have 263 scanlines,
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// and odd frames have 262 scanlines.
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// Interlace mode scanline 240 on odd frames is not missing a dot.
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if (CPU.V_Counter == 240 && !IPPU.Interlace && Timings.InterlaceField) // V=240
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Timings.H_Max = Timings.H_Max_Master - ONE_DOT_CYCLE; // HC=1360
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else
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Timings.H_Max = Timings.H_Max_Master; // HC=1364
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if (Model->_5A22 == 2)
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{
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if (CPU.V_Counter != 240 || IPPU.Interlace || !Timings.InterlaceField) // V=240
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{
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if (Timings.WRAMRefreshPos == SNES_WRAM_REFRESH_HC_v2 - ONE_DOT_CYCLE) // HC=534
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2; // HC=538
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else
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2 - ONE_DOT_CYCLE; // HC=534
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}
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}
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else
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v1;
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S9xCheckMissingHTimerPosition(0);
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if (CPU.V_Counter == PPU.ScreenHeight + FIRST_VISIBLE_LINE) // VBlank starts from V=225(240).
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{
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S9xEndScreenRefresh();
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PPU.HDMA = 0;
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// Bits 7 and 6 of $4212 are computed when read in S9xGetPPU.
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#ifdef DEBUGGER
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missing.dma_this_frame = 0;
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#endif
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IPPU.MaxBrightness = PPU.Brightness;
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PPU.ForcedBlanking = (Memory.FillRAM [0x2100] >> 7) & 1;
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if (!PPU.ForcedBlanking)
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{
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PPU.OAMAddr = PPU.SavedOAMAddr;
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uint8 tmp = 0;
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if (PPU.OAMPriorityRotation)
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tmp = (PPU.OAMAddr & 0xFE) >> 1;
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if ((PPU.OAMFlip & 1) || PPU.FirstSprite!=tmp)
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{
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PPU.FirstSprite = tmp;
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IPPU.OBJChanged = TRUE;
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}
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PPU.OAMFlip = 0;
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}
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// FIXME: writing to $4210 will wait 6 cycles.
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Memory.FillRAM[0x4210] = 0x80 | Model->_5A22;
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if (Memory.FillRAM[0x4200] & 0x80)
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{
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// FIXME: triggered at HC=6, checked just before the final CPU cycle,
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// then, when to call S9xOpcode_NMI()?
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CPU.Flags |= NMI_FLAG;
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Timings.NMITriggerPos = 6 + 6;
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}
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}
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if (CPU.V_Counter == PPU.ScreenHeight + 3) // FIXME: not true
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{
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if (Memory.FillRAM[0x4200] & 1)
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S9xDoAutoJoypad();
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}
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if (CPU.V_Counter == FIRST_VISIBLE_LINE) // V=1
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S9xStartScreenRefresh();
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CPU.NextEvent = -1;
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break;
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case HC_HDMA_INIT_EVENT:
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if (CPU.V_Counter == 0)
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S9xStartHDMA();
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S9xCheckMissingHTimerPosition(Timings.HDMAInit);
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break;
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case HC_RENDER_EVENT:
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if (CPU.V_Counter >= FIRST_VISIBLE_LINE && CPU.V_Counter <= PPU.ScreenHeight)
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RenderLine((uint8)(CPU.V_Counter - FIRST_VISIBLE_LINE));
|
|
|
|
S9xCheckMissingHTimerPosition(Timings.RenderPos);
|
|
|
|
break;
|
|
|
|
case HC_WRAM_REFRESH_EVENT:
|
|
#ifdef DEBUGGER
|
|
sprintf(mes, "*** WRAM Refresh HC:%04d", CPU.Cycles);
|
|
S9xTraceMessage(mes);
|
|
#endif
|
|
S9xCheckMissingHTimerHalt(Timings.WRAMRefreshPos, SNES_WRAM_REFRESH_CYCLES);
|
|
CPU.Cycles += SNES_WRAM_REFRESH_CYCLES;
|
|
S9xAPUExecute();
|
|
|
|
S9xCheckMissingHTimerPosition(Timings.WRAMRefreshPos);
|
|
|
|
break;
|
|
|
|
case HC_IRQ_1_3_EVENT:
|
|
case HC_IRQ_3_5_EVENT:
|
|
case HC_IRQ_5_7_EVENT:
|
|
case HC_IRQ_7_9_EVENT:
|
|
case HC_IRQ_9_A_EVENT:
|
|
case HC_IRQ_A_1_EVENT:
|
|
if (PPU.HTimerEnabled && (!PPU.VTimerEnabled || (CPU.V_Counter == PPU.VTimerPosition)))
|
|
S9xSetIRQ(PPU_H_BEAM_IRQ_SOURCE);
|
|
else
|
|
if (PPU.VTimerEnabled && (CPU.V_Counter == PPU.VTimerPosition))
|
|
S9xSetIRQ(PPU_V_BEAM_IRQ_SOURCE);
|
|
|
|
break;
|
|
}
|
|
|
|
S9xReschedule();
|
|
}
|