mirror of
https://github.com/dborth/snes9xgx.git
synced 2024-12-26 19:21:50 +01:00
adf61aef32
- Fixed invalid memory accesses in C4 and OBC1. MMX3 Toxic Seahorse stage now can be emulated with HDMA. (zones) - Updated snapshot to prevent desync. Added some variables related to APU and HDMA. (gocha)
956 lines
29 KiB
C
956 lines
29 KiB
C
/**********************************************************************************
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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(c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com),
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Jerremy Koot (jkoot@snes9x.com)
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(c) Copyright 2002 - 2004 Matthew Kendora
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(c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org)
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(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
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(c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net)
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(c) Copyright 2002 - 2006 funkyass (funkyass@spam.shaw.ca),
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Kris Bleakley (codeviolation@hotmail.com)
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(c) Copyright 2002 - 2007 Brad Jorsch (anomie@users.sourceforge.net),
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Nach (n-a-c-h@users.sourceforge.net),
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zones (kasumitokoduck@yahoo.com)
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(c) Copyright 2006 - 2007 nitsuja
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BS-X C emulator code
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(c) Copyright 2005 - 2006 Dreamer Nom,
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zones
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C4 x86 assembler and some C emulation code
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(c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com),
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Nach,
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zsKnight (zsknight@zsnes.com)
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C4 C++ code
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(c) Copyright 2003 - 2006 Brad Jorsch,
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Nach
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DSP-1 emulator code
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(c) Copyright 1998 - 2006 _Demo_,
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Andreas Naive (andreasnaive@gmail.com)
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Gary Henderson,
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Ivar (ivar@snes9x.com),
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John Weidman,
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Kris Bleakley,
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Matthew Kendora,
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Nach,
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neviksti (neviksti@hotmail.com)
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DSP-2 emulator code
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(c) Copyright 2003 John Weidman,
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Kris Bleakley,
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Lord Nightmare (lord_nightmare@users.sourceforge.net),
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Matthew Kendora,
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neviksti
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DSP-3 emulator code
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(c) Copyright 2003 - 2006 John Weidman,
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Kris Bleakley,
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Lancer,
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z80 gaiden
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DSP-4 emulator code
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(c) Copyright 2004 - 2006 Dreamer Nom,
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John Weidman,
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Kris Bleakley,
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Nach,
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z80 gaiden
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OBC1 emulator code
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(c) Copyright 2001 - 2004 zsKnight,
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pagefault (pagefault@zsnes.com),
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Kris Bleakley,
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Ported from x86 assembler to C by sanmaiwashi
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SPC7110 and RTC C++ emulator code
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(c) Copyright 2002 Matthew Kendora with research by
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zsKnight,
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John Weidman,
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Dark Force
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S-DD1 C emulator code
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(c) Copyright 2003 Brad Jorsch with research by
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Andreas Naive,
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John Weidman
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S-RTC C emulator code
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(c) Copyright 2001-2006 byuu,
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John Weidman
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ST010 C++ emulator code
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(c) Copyright 2003 Feather,
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John Weidman,
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Kris Bleakley,
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Matthew Kendora
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Super FX x86 assembler emulator code
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(c) Copyright 1998 - 2003 _Demo_,
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pagefault,
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zsKnight,
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Super FX C emulator code
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(c) Copyright 1997 - 1999 Ivar,
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Gary Henderson,
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John Weidman
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Sound DSP emulator code is derived from SNEeSe and OpenSPC:
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(c) Copyright 1998 - 2003 Brad Martin
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(c) Copyright 1998 - 2006 Charles Bilyue'
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SH assembler code partly based on x86 assembler code
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(c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se)
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2xSaI filter
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(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
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HQ2x, HQ3x, HQ4x filters
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(c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com)
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Win32 GUI code
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(c) Copyright 2003 - 2006 blip,
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funkyass,
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Matthew Kendora,
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Nach,
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nitsuja
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Mac OS GUI code
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(c) Copyright 1998 - 2001 John Stiles
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(c) Copyright 2001 - 2007 zones
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Specific ports contains the works of other authors. See headers in
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individual files.
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Snes9x homepage: http://www.snes9x.com
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Permission to use, copy, modify and/or distribute Snes9x in both binary
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and source form, for non-commercial purposes, is hereby granted without
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fee, providing that this license information and copyright notice appear
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with all copies and any derived work.
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This software is provided 'as-is', without any express or implied
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warranty. In no event shall the authors be held liable for any damages
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arising from the use of this software or it's derivatives.
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Snes9x is freeware for PERSONAL USE only. Commercial users should
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seek permission of the copyright holders first. Commercial use includes,
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but is not limited to, charging money for Snes9x or software derived from
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Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
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using Snes9x as a promotion for your commercial product.
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The copyright holders request that bug fixes and improvements to the code
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should be forwarded to them so everyone can benefit from the modifications
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in future versions.
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Super NES and Super Nintendo Entertainment System are trademarks of
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Nintendo Co., Limited and its subsidiary companies.
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**********************************************************************************/
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#ifndef _GETSET_H_
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#define _GETSET_H_
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#include "ppu.h"
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#include "dsp1.h"
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#include "cpuexec.h"
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#include "sa1.h"
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#include "spc7110.h"
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#include "obc1.h"
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#include "seta.h"
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#include "bsx.h"
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extern "C"
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{
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extern uint8 OpenBus;
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}
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INLINE uint8 S9xGetByte (uint32 Address)
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{
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int block;
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uint8 *GetAddress = Memory.Map [block = ((Address&0xffffff) >> MEMMAP_SHIFT)];
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if(!CPU.InDMAorHDMA)
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CPU.Cycles += Memory.MemorySpeed [block];
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if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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#ifdef CPU_SHUTDOWN
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if (Memory.BlockIsRAM [block])
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CPU.WaitAddress = CPU.PBPCAtOpcodeStart;
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#endif
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return (*(GetAddress + (Address & 0xffff)));
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}
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switch ((pint) GetAddress)
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{
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case CMemory::MAP_PPU:
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if(CPU.InDMAorHDMA && (Address&0xff00)==0x2100) return OpenBus;
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return (S9xGetPPU (Address & 0xffff));
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case CMemory::MAP_CPU:
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return (S9xGetCPU (Address & 0xffff));
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case CMemory::MAP_DSP:
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return (S9xGetDSP (Address & 0xffff));
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case CMemory::MAP_SA1RAM:
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case CMemory::MAP_LOROM_SRAM:
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//Address &0x7FFF -offset into bank
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//Address&0xFF0000 -bank
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//bank>>1 | offset = s-ram address, unbound
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//unbound & SRAMMask = Sram offset
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return (*(Memory.SRAM + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Memory.SRAMMask)));
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case CMemory::MAP_LOROM_SRAM_B:
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return (*(Multi.sramB + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Multi.sramMaskB)));
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case CMemory::MAP_RONLY_SRAM:
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case CMemory::MAP_HIROM_SRAM:
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return (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
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((Address & 0xf0000) >> 3)) & Memory.SRAMMask)));
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case CMemory::MAP_BWRAM:
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return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)));
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case CMemory::MAP_C4:
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return (S9xGetC4 (Address & 0xffff));
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case CMemory::MAP_SPC7110_ROM:
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#ifdef SPC7110_DEBUG
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printf("reading spc7110 ROM (byte) at %06X\n", Address);
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#endif
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return S9xGetSPC7110Byte(Address);
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case CMemory::MAP_SPC7110_DRAM:
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#ifdef SPC7110_DEBUG
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printf("reading Bank 50 (byte)\n");
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#endif
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return S9xGetSPC7110(0x4800);
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case CMemory::MAP_OBC_RAM:
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return GetOBC1(Address & 0xffff);
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case CMemory::MAP_SETA_DSP:
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return S9xGetSetaDSP(Address);
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case CMemory::MAP_SETA_RISC:
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return S9xGetST018(Address);
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case CMemory::MAP_BSX:
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return S9xGetBSX(Address);
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case CMemory::MAP_DEBUG:
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#ifdef DEBUGGER
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printf ("DEBUG R(B) %06x\n", Address);
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#endif
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default:
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case CMemory::MAP_NONE:
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return OpenBus;
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}
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}
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#ifdef NO_INLINE_SET_GET
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INLINE uint16 S9xGetWord (uint32 Address, enum s9xwrap_t w)
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#else
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INLINE uint16 S9xGetWord (uint32 Address, enum s9xwrap_t w=WRAP_NONE)
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#endif
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{
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uint32 mask=MEMMAP_MASK&(w==WRAP_PAGE?0xff:(w==WRAP_BANK?0xffff:0xffffff));
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if ((Address & mask) == mask)
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{
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OpenBus=S9xGetByte(Address);
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switch(w){
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case WRAP_PAGE:
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{
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PC_t a;
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a.xPBPC = Address;
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a.B.xPCl++;
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return (OpenBus | (S9xGetByte (a.xPBPC) << 8));
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}
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case WRAP_BANK:
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{
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PC_t a;
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a.xPBPC = Address;
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a.W.xPC++;
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return (OpenBus | (S9xGetByte (a.xPBPC) << 8));
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}
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case WRAP_NONE:
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default:
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return (OpenBus | (S9xGetByte (Address + 1) << 8));
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}
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}
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int block;
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uint8 *GetAddress = Memory.Map [block = ((Address&0xffffff) >> MEMMAP_SHIFT)];
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if(!CPU.InDMAorHDMA)
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CPU.Cycles += (Memory.MemorySpeed [block]<<1);
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if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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#ifdef CPU_SHUTDOWN
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if (Memory.BlockIsRAM [block])
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CPU.WaitAddress = CPU.PBPCAtOpcodeStart;
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#endif
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return READ_WORD(GetAddress + (Address & 0xffff));
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}
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switch ((pint) GetAddress)
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{
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case CMemory::MAP_PPU:
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if(CPU.InDMAorHDMA){
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OpenBus=S9xGetByte (Address);
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return (OpenBus | (S9xGetByte (Address + 1) << 8));
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}
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return (S9xGetPPU (Address & 0xffff) |
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(S9xGetPPU ((Address + 1) & 0xffff) << 8));
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case CMemory::MAP_CPU:
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return (S9xGetCPU (Address & 0xffff) |
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(S9xGetCPU ((Address + 1) & 0xffff) << 8));
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case CMemory::MAP_DSP:
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#ifdef DSP_DUMMY_LOOPS
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printf("Get DSP Word @ %06X\n", Address);
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#endif
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return (S9xGetDSP (Address & 0xffff) |
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(S9xGetDSP ((Address + 1) & 0xffff) << 8));
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case CMemory::MAP_SA1RAM:
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case CMemory::MAP_LOROM_SRAM:
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//Address &0x7FFF -offset into bank
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//Address&0xFF0000 -bank
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//bank>>1 | offset = s-ram address, unbound
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//unbound & SRAMMask = Sram offset
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if(Memory.SRAMMask>=MEMMAP_MASK){
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return READ_WORD(Memory.SRAM + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Memory.SRAMMask));
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} else {
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/* no READ_WORD here, since if Memory.SRAMMask=0x7ff
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* then the high byte doesn't follow the low byte. */
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return
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(*(Memory.SRAM + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Memory.SRAMMask)))|
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((*(Memory.SRAM + (((((Address+1)&0xFF0000)>>1) |((Address+1)&0x7FFF)) &Memory.SRAMMask)))<<8);
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}
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case CMemory::MAP_LOROM_SRAM_B:
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if(Multi.sramMaskB>=MEMMAP_MASK){
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return READ_WORD(Multi.sramB + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Multi.sramMaskB));
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} else {
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return
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(*(Multi.sramB + ((((Address&0xFF0000)>>1) |(Address&0x7FFF)) &Multi.sramMaskB)))|
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((*(Multi.sramB + (((((Address+1)&0xFF0000)>>1) |((Address+1)&0x7FFF)) &Multi.sramMaskB)))<<8);
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}
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case CMemory::MAP_RONLY_SRAM:
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case CMemory::MAP_HIROM_SRAM:
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if(Memory.SRAMMask>=MEMMAP_MASK){
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return READ_WORD(Memory.SRAM +
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(((Address & 0x7fff) - 0x6000 +
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((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
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} else {
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/* no READ_WORD here, since if Memory.SRAMMask=0x7ff
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* then the high byte doesn't follow the low byte. */
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return (*(Memory.SRAM +
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(((Address & 0x7fff) - 0x6000 +
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((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) |
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(*(Memory.SRAM +
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((((Address + 1) & 0x7fff) - 0x6000 +
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(((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) << 8));
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}
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case CMemory::MAP_BWRAM:
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return READ_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000));
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case CMemory::MAP_C4:
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return (S9xGetC4 (Address & 0xffff) |
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(S9xGetC4 ((Address + 1) & 0xffff) << 8));
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case CMemory::MAP_SPC7110_ROM:
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#ifdef SPC7110_DEBUG
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printf("reading spc7110 ROM (word) at %06X\n", Address);
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#endif
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return (S9xGetSPC7110Byte(Address)|
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(S9xGetSPC7110Byte (Address+1))<<8);
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case CMemory::MAP_SPC7110_DRAM:
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#ifdef SPC7110_DEBUG
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printf("reading Bank 50 (word)\n");
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#endif
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return (S9xGetSPC7110(0x4800)|
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(S9xGetSPC7110 (0x4800) << 8));
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case CMemory::MAP_OBC_RAM:
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return GetOBC1(Address&0xFFFF)| (GetOBC1((Address+1)&0xFFFF)<<8);
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case CMemory::MAP_SETA_DSP:
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return S9xGetSetaDSP(Address)| (S9xGetSetaDSP((Address+1))<<8);
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case CMemory::MAP_SETA_RISC:
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return S9xGetST018(Address)| (S9xGetST018((Address+1))<<8);
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case CMemory::MAP_BSX:
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return S9xGetBSX(Address)| (S9xGetBSX((Address+1))<<8);
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case CMemory::MAP_DEBUG:
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#ifdef DEBUGGER
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printf ("DEBUG R(W) %06x\n", Address);
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#endif
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default:
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case CMemory::MAP_NONE:
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return (OpenBus | (OpenBus<<8));
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}
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}
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INLINE void S9xSetByte (uint8 Byte, uint32 Address)
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{
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#if defined(CPU_SHUTDOWN)
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CPU.WaitAddress = 0xffffffff;
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#endif
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int block;
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uint8 *SetAddress = Memory.WriteMap [block = ((Address&0xffffff) >> MEMMAP_SHIFT)];
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if (!CPU.InDMAorHDMA)
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CPU.Cycles += Memory.MemorySpeed [block];
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if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
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{
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#ifdef CPU_SHUTDOWN
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SetAddress += Address & 0xffff;
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if (SetAddress == SA1.WaitByteAddress1 ||
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SetAddress == SA1.WaitByteAddress2)
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{
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SA1.Executing = SA1.S9xOpcodes != NULL;
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SA1.WaitCounter = 0;
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}
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*SetAddress = Byte;
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#else
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*(SetAddress + (Address & 0xffff)) = Byte;
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#endif
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return;
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}
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switch ((pint) SetAddress)
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{
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case CMemory::MAP_PPU:
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if(CPU.InDMAorHDMA && (Address&0xff00)==0x2100) return;
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S9xSetPPU (Byte, Address & 0xffff);
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return;
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case CMemory::MAP_CPU:
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S9xSetCPU (Byte, Address & 0xffff);
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return;
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case CMemory::MAP_DSP:
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#ifdef DSP_DUMMY_LOOPS
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printf("DSP Byte: %02X to %06X\n", Byte, Address);
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#endif
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S9xSetDSP (Byte, Address & 0xffff);
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return;
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case CMemory::MAP_LOROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))& Memory.SRAMMask))=Byte;
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CPU.SRAMModified = TRUE;
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}
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return;
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case CMemory::MAP_LOROM_SRAM_B:
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if (Multi.sramMaskB)
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{
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*(Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))& Multi.sramMaskB))=Byte;
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CPU.SRAMModified = TRUE;
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}
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return;
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case CMemory::MAP_HIROM_SRAM:
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if (Memory.SRAMMask)
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{
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*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
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((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = Byte;
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CPU.SRAMModified = TRUE;
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}
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return;
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case CMemory::MAP_BWRAM:
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*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
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CPU.SRAMModified = TRUE;
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return;
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case CMemory::MAP_SA1RAM:
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*(Memory.SRAM + (Address & 0xffff)) = Byte;
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SA1.Executing = !SA1.Waiting;
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break;
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case CMemory::MAP_C4:
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S9xSetC4 (Byte, Address & 0xffff);
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return;
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case CMemory::MAP_SPC7110_DRAM:
|
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#ifdef SPC7110_DEBUG
|
|
printf("Writing Byte at %06X\n", Address);
|
|
#endif
|
|
s7r.bank50[(Address & 0xffff)]= (uint8) Byte;
|
|
break;
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
SetOBC1(Byte, Address &0xFFFF);
|
|
return;
|
|
|
|
case CMemory::MAP_SETA_DSP:
|
|
S9xSetSetaDSP(Byte,Address);
|
|
return;
|
|
|
|
case CMemory::MAP_SETA_RISC:
|
|
S9xSetST018(Byte,Address);
|
|
return;
|
|
|
|
case CMemory::MAP_BSX:
|
|
S9xSetBSX(Byte,Address);
|
|
return;
|
|
|
|
case CMemory::MAP_DEBUG:
|
|
#ifdef DEBUGGER
|
|
printf ("W(B) %06x\n", Address);
|
|
#endif
|
|
default:
|
|
case CMemory::MAP_NONE:
|
|
return;
|
|
}
|
|
}
|
|
|
|
#ifdef NO_INLINE_SET_GET
|
|
INLINE void S9xSetWord (uint16 Word, uint32 Address, enum s9xwrap_t w, enum s9xwriteorder_t o)
|
|
#else
|
|
INLINE void S9xSetWord (uint16 Word, uint32 Address, enum s9xwrap_t w=WRAP_NONE, enum s9xwriteorder_t o=WRITE_01)
|
|
#endif
|
|
{
|
|
uint32 mask=MEMMAP_MASK&(w==WRAP_PAGE?0xff:(w==WRAP_BANK?0xffff:0xffffff));
|
|
if ((Address & mask) == mask)
|
|
{
|
|
if(!o) S9xSetByte(Word&0x00FF, Address);
|
|
switch(w){
|
|
case WRAP_PAGE:
|
|
{
|
|
PC_t a;
|
|
a.xPBPC = Address;
|
|
a.B.xPCl++;
|
|
S9xSetByte(Word>>8, a.xPBPC);
|
|
}
|
|
case WRAP_BANK:
|
|
{
|
|
PC_t a;
|
|
a.xPBPC = Address;
|
|
a.W.xPC++;
|
|
S9xSetByte(Word>>8, a.xPBPC);
|
|
}
|
|
case WRAP_NONE:
|
|
default:
|
|
S9xSetByte(Word>>8, Address+1);
|
|
}
|
|
if(o) S9xSetByte(Word&0x00FF, Address);
|
|
return;
|
|
}
|
|
|
|
#if defined(CPU_SHUTDOWN)
|
|
CPU.WaitAddress = 0xffffffff;
|
|
#endif
|
|
int block;
|
|
uint8 *SetAddress = Memory.WriteMap [block = ((Address&0xffffff) >> MEMMAP_SHIFT)];
|
|
|
|
if (!CPU.InDMAorHDMA)
|
|
CPU.Cycles += Memory.MemorySpeed [block] << 1;
|
|
|
|
|
|
if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
{
|
|
#ifdef CPU_SHUTDOWN
|
|
SetAddress += Address & 0xffff;
|
|
if (SetAddress == SA1.WaitByteAddress1 ||
|
|
SetAddress == SA1.WaitByteAddress2)
|
|
{
|
|
SA1.Executing = SA1.S9xOpcodes != NULL;
|
|
SA1.WaitCounter = 0;
|
|
}
|
|
WRITE_WORD(SetAddress, Word);
|
|
#else
|
|
WRITE_WORD(SetAddress + (Address & 0xffff), Word);
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
switch ((pint) SetAddress)
|
|
{
|
|
case CMemory::MAP_PPU:
|
|
if(CPU.InDMAorHDMA){
|
|
if((Address&0xff00)!=0x2100) S9xSetPPU((uint8)Word, Address&0xffff);
|
|
if(((Address+1)&0xff00)!=0x2100) S9xSetPPU(Word>>8, (Address+1)&0xffff);
|
|
return;
|
|
}
|
|
if(o){
|
|
S9xSetPPU (Word >> 8, (Address & 0xffff) + 1);
|
|
S9xSetPPU ((uint8) Word, Address & 0xffff);
|
|
} else {
|
|
S9xSetPPU ((uint8) Word, Address & 0xffff);
|
|
S9xSetPPU (Word >> 8, (Address & 0xffff) + 1);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_CPU:
|
|
if(o){
|
|
S9xSetCPU (Word >> 8, (Address & 0xffff) + 1);
|
|
S9xSetCPU ((uint8) Word, (Address & 0xffff));
|
|
} else {
|
|
S9xSetCPU ((uint8) Word, (Address & 0xffff));
|
|
S9xSetCPU (Word >> 8, (Address & 0xffff) + 1);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_DSP:
|
|
#ifdef DSP_DUMMY_LOOPS
|
|
printf("DSP Word: %04X to %06X\n", Word, Address);
|
|
#endif
|
|
if(o){
|
|
S9xSetDSP (Word >> 8, (Address & 0xffff) + 1);
|
|
S9xSetDSP ((uint8) Word, (Address & 0xffff));
|
|
} else {
|
|
S9xSetDSP ((uint8) Word, (Address & 0xffff));
|
|
S9xSetDSP (Word >> 8, (Address & 0xffff) + 1);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if (Memory.SRAMMask) {
|
|
if(Memory.SRAMMask>=MEMMAP_MASK){
|
|
WRITE_WORD(Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))&Memory.SRAMMask), Word);
|
|
} else {
|
|
/* no WRITE_WORD here, since if Memory.SRAMMask=0x7ff
|
|
* then the high byte doesn't follow the low byte. */
|
|
*(Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))& Memory.SRAMMask)) = (uint8) Word;
|
|
*(Memory.SRAM + (((((Address+1)&0xFF0000)>>1)|((Address+1)&0x7FFF))& Memory.SRAMMask)) = Word >> 8;
|
|
}
|
|
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if (Multi.sramMaskB) {
|
|
if(Multi.sramMaskB>=MEMMAP_MASK){
|
|
WRITE_WORD(Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))&Multi.sramMaskB), Word);
|
|
} else {
|
|
*(Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF))& Multi.sramMaskB)) = (uint8) Word;
|
|
*(Multi.sramB + (((((Address+1)&0xFF0000)>>1)|((Address+1)&0x7FFF))& Multi.sramMaskB)) = Word >> 8;
|
|
}
|
|
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if (Memory.SRAMMask) {
|
|
if(Memory.SRAMMask>=MEMMAP_MASK){
|
|
WRITE_WORD(Memory.SRAM +
|
|
(((Address & 0x7fff) - 0x6000 +
|
|
((Address & 0xf0000) >> 3) & Memory.SRAMMask)), Word);
|
|
} else {
|
|
/* no WRITE_WORD here, since if Memory.SRAMMask=0x7ff
|
|
* then the high byte doesn't follow the low byte. */
|
|
*(Memory.SRAM +
|
|
(((Address & 0x7fff) - 0x6000 +
|
|
((Address & 0xf0000) >> 3) & Memory.SRAMMask))) = (uint8) Word;
|
|
*(Memory.SRAM +
|
|
((((Address + 1) & 0x7fff) - 0x6000 +
|
|
(((Address + 1) & 0xf0000) >> 3) & Memory.SRAMMask))) = (uint8) (Word >> 8);
|
|
}
|
|
CPU.SRAMModified = TRUE;
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
WRITE_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000), Word);
|
|
CPU.SRAMModified = TRUE;
|
|
return;
|
|
|
|
case CMemory::MAP_SPC7110_DRAM:
|
|
#ifdef SPC7110_DEBUG
|
|
printf("Writing Word at %06X\n", Address);
|
|
#endif
|
|
WRITE_WORD(s7r.bank50+(Address & 0xffff), Word);
|
|
break;
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
WRITE_WORD(Memory.SRAM + (Address & 0xffff), Word);
|
|
SA1.Executing = !SA1.Waiting;
|
|
break;
|
|
|
|
case CMemory::MAP_C4:
|
|
if(o){
|
|
S9xSetC4 ((uint8) (Word >> 8), (Address + 1) & 0xffff);
|
|
S9xSetC4 (Word & 0xff, Address & 0xffff);
|
|
} else {
|
|
S9xSetC4 (Word & 0xff, Address & 0xffff);
|
|
S9xSetC4 ((uint8) (Word >> 8), (Address + 1) & 0xffff);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
if(o){
|
|
SetOBC1((uint8) (Word >> 8), (Address + 1) & 0xffff);
|
|
SetOBC1(Word & 0xff, Address &0xFFFF);
|
|
} else {
|
|
SetOBC1(Word & 0xff, Address &0xFFFF);
|
|
SetOBC1 ((uint8) (Word >> 8), (Address + 1) & 0xffff);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_SETA_DSP:
|
|
if(o){
|
|
S9xSetSetaDSP ((uint8) (Word >> 8),(Address + 1));
|
|
S9xSetSetaDSP (Word & 0xff, Address);
|
|
} else {
|
|
S9xSetSetaDSP (Word & 0xff, Address);
|
|
S9xSetSetaDSP ((uint8) (Word >> 8),(Address + 1));
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_SETA_RISC:
|
|
if(o){
|
|
S9xSetST018 ((uint8) (Word >> 8),(Address + 1));
|
|
S9xSetST018 (Word & 0xff, Address);
|
|
} else {
|
|
S9xSetST018 (Word & 0xff, Address);
|
|
S9xSetST018 ((uint8) (Word >> 8),(Address + 1));
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_BSX:
|
|
if(o){
|
|
S9xSetBSX ((uint8) (Word >> 8),(Address + 1));
|
|
S9xSetBSX (Word & 0xff, Address);
|
|
} else {
|
|
S9xSetBSX (Word & 0xff, Address);
|
|
S9xSetBSX ((uint8) (Word >> 8),(Address + 1));
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_DEBUG:
|
|
#ifdef DEBUGGER
|
|
printf ("W(W) %06x\n", Address);
|
|
#endif
|
|
default:
|
|
case CMemory::MAP_NONE:
|
|
return;
|
|
}
|
|
}
|
|
|
|
INLINE uint8 *GetBasePointer (uint32 Address)
|
|
{
|
|
uint8 *GetAddress = Memory.Map [((Address&0xffffff) >> MEMMAP_SHIFT)];
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
return (GetAddress);
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
// case CMemory::MAP_SPC7110_DRAM:
|
|
#ifdef SPC7110_DEBUG
|
|
// printf("Getting Base pointer to DRAM\n");
|
|
#endif
|
|
// {
|
|
// return s7r.bank50;
|
|
// }
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
#ifdef SPC7110_DEBUG
|
|
printf("Getting Base pointer to SPC7110ROM\n");
|
|
#endif
|
|
return Get7110BasePtr(Address);
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
return (Memory.SRAM);
|
|
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Memory.SRAMMask) - (Address&0xffff));
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if((Multi.sramMaskB&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Multi.sramMaskB) - (Address&0xffff));
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
return (Memory.BWRAM - 0x6000 - (Address&0x8000));
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address&0xffff));
|
|
|
|
case CMemory::MAP_C4:
|
|
return (S9xGetBasePointerC4(Address & 0xffff));
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
return (S9xGetBasePointerOBC1(Address & 0xffff));
|
|
|
|
case CMemory::MAP_DEBUG:
|
|
#ifdef DEBUGGER
|
|
printf ("GBP %06x\n", Address);
|
|
#endif
|
|
default:
|
|
case CMemory::MAP_NONE:
|
|
return (0);
|
|
}
|
|
}
|
|
|
|
INLINE uint8 *S9xGetMemPointer (uint32 Address)
|
|
{
|
|
uint8 *GetAddress = Memory.Map [((Address&0xffffff) >> MEMMAP_SHIFT)];
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
|
|
return (GetAddress + (Address&0xffff));
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
// case CMemory::MAP_SPC7110_DRAM:
|
|
#ifdef SPC7110_DEBUG
|
|
// printf("Getting Mem pointer to DRAM\n");
|
|
#endif
|
|
// {
|
|
// return s7r.bank50 + (Address&0xffff);
|
|
// }
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
#ifdef SPC7110_DEBUG
|
|
printf("Getting Mem pointer to SPC7110ROM\n");
|
|
#endif
|
|
return Get7110BasePtr(Address) + (Address&0xffff);
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
return (Memory.SRAM + (Address&0xffff));
|
|
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Memory.SRAMMask));
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if((Multi.sramMaskB&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Multi.sramMaskB));
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
return (Memory.BWRAM - 0x6000 + (Address&0x7fff));
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK) return NULL;
|
|
return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask));
|
|
|
|
case CMemory::MAP_C4:
|
|
return (S9xGetMemPointerC4(Address & 0xffff));
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
return (S9xGetMemPointerOBC1(Address & 0xffff));
|
|
|
|
case CMemory::MAP_DEBUG:
|
|
#ifdef DEBUGGER
|
|
printf ("GMP %06x\n", Address);
|
|
#endif
|
|
default:
|
|
case CMemory::MAP_NONE:
|
|
return (0);
|
|
}
|
|
}
|
|
|
|
INLINE void S9xSetPCBase (uint32 Address)
|
|
{
|
|
Registers.PBPC = Address & 0xffffff;
|
|
ICPU.ShiftedPB = Address & 0xff0000;
|
|
|
|
int block;
|
|
uint8 *GetAddress = Memory.Map [block = ((Address&0xffffff) >> MEMMAP_SHIFT)];
|
|
|
|
CPU.MemSpeed = Memory.MemorySpeed [block];
|
|
CPU.MemSpeedx2 = CPU.MemSpeed << 1;
|
|
|
|
if (GetAddress >= (uint8 *) CMemory::MAP_LAST){
|
|
CPU.PCBase = GetAddress;
|
|
return;
|
|
}
|
|
|
|
switch ((pint) GetAddress)
|
|
{
|
|
// case CMemory::MAP_SPC7110_DRAM:
|
|
#ifdef SPC7110_DEBUG
|
|
// printf("Getting Base pointer to DRAM\n");
|
|
#endif
|
|
// {
|
|
// CPU.PCBase = s7r.bank50;
|
|
// return;
|
|
// }
|
|
|
|
case CMemory::MAP_SPC7110_ROM:
|
|
#ifdef SPC7110_DEBUG
|
|
printf("Getting Base pointer to SPC7110ROM\n");
|
|
#endif
|
|
CPU.PCBase = Get7110BasePtr(Address);
|
|
return;
|
|
|
|
case CMemory::MAP_SA1RAM:
|
|
CPU.PCBase = Memory.SRAM;
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK){
|
|
CPU.PCBase = NULL;
|
|
} else {
|
|
CPU.PCBase = (Memory.SRAM + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Memory.SRAMMask)) - (Address&0xffff);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_LOROM_SRAM_B:
|
|
if((Multi.sramMaskB&MEMMAP_MASK)!=MEMMAP_MASK){
|
|
CPU.PCBase = NULL;
|
|
} else {
|
|
CPU.PCBase = (Multi.sramB + ((((Address&0xFF0000)>>1)|(Address&0x7FFF)) & Multi.sramMaskB)) - (Address&0xffff);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_BWRAM:
|
|
CPU.PCBase = (Memory.BWRAM - 0x6000 - (Address&0x8000));
|
|
return;
|
|
|
|
case CMemory::MAP_HIROM_SRAM:
|
|
if((Memory.SRAMMask&MEMMAP_MASK)!=MEMMAP_MASK){
|
|
CPU.PCBase = NULL;
|
|
} else {
|
|
CPU.PCBase = (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) - (Address&0xffff);
|
|
}
|
|
return;
|
|
|
|
case CMemory::MAP_C4:
|
|
CPU.PCBase = S9xGetBasePointerC4(Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_OBC_RAM:
|
|
CPU.PCBase = S9xGetBasePointerOBC1(Address & 0xffff);
|
|
return;
|
|
|
|
case CMemory::MAP_BSX:
|
|
CPU.PCBase = S9xGetBasePointerBSX(Address);
|
|
return;
|
|
|
|
case CMemory::MAP_DEBUG:
|
|
#ifdef DEBUGGER
|
|
printf ("SBP %06x\n", Address);
|
|
#endif
|
|
default:
|
|
case CMemory::MAP_NONE:
|
|
CPU.PCBase = NULL;
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
|