198 Commits

Author SHA1 Message Date
Chris Siebert
af88dd022d Update README.md
Small formatting correction with the APU Register Activation error codes.
2025-06-06 22:09:19 -04:00
Chris Siebert
7008b224fa Update README.md
Added 2 more tests to APU Register Activation
2025-06-06 22:02:03 -04:00
100thCoin
9d552e8e21 Merge branch 'main' of https://github.com/100thCoin/AccuracyCoin 2025-06-06 21:59:34 -04:00
100thCoin
7cd96b53d1 Extended the APU Register Activation test
This test now tests for bus conflicts, if the DMA happens on page 2 instead of page $40
2025-06-06 21:59:30 -04:00
Chris Siebert
e3fefe148e Update README.md
Added an example screenshot of the main screen.
2025-06-06 17:27:38 -04:00
Chris Siebert
3edc248021 Update README.md
Added a section about navigating the menus to the README, as well as adding an example image of the "All test table".
2025-06-06 17:22:26 -04:00
Chris Siebert
0691c81f62 Update README.md
Made a correction to the error codes for the SHS and LAE tests.
2025-06-06 17:11:38 -04:00
100thCoin
4863fd50b9 Merge branch 'main' of https://github.com/100thCoin/AccuracyCoin 2025-06-06 17:07:14 -04:00
100thCoin
35904bcfd1 Fixed typos, added comments, moved a test.
I moved the Unofficial instruction test to the bottom of page 1.
2025-06-06 17:06:52 -04:00
Chris Siebert
ce85ce7b55 Update README.md
Added an explanation for every error code currently in the ROM.
2025-06-06 17:03:52 -04:00
100thCoin
1a781f555e Added more comments
Added more comments
2025-06-06 14:10:32 -04:00
100thCoin
0f1bbd36f2 Added more comments and fixed some typos 2025-06-06 13:45:20 -04:00
100thCoin
19229b9b76 Fixed an issue with Dummy Write Cycles
Added more comments, and failing the ppu open bus test will not affect the error code of Dummy Write Cycles.
2025-06-06 11:31:27 -04:00
100thCoin
8cdcc7f7fa Updated the DMA + 4015 test to actually work.
The Frame counter interrupt flag was getting cleared inside the DMA Sync routine, so this fixes that.
2025-06-06 02:04:09 -04:00
100thCoin
ea4de9b3ad Updates PPU Open Bus test.
Added a test for bits decaying.
2025-06-06 01:07:15 -04:00
100thCoin
bc131480cb Updates the run-all-test menu
The run-all-test menu now omits "print" tests that don't actually test for anything.
2025-06-05 23:29:47 -04:00
100thCoin
f7bbba84a7 Added the Automatic-All-Test-Menu
By pressing Start, it automatically runs every test in the ROM, then prints the results in a table.
2025-06-05 02:13:00 -04:00
100thCoin
79d222cf1c Added a test for DMA plus Open Bus.
Added a test for DMA plus Open Bus.
Removed some unnecessary comments from the DMA bus conflict test.
2025-06-04 02:31:27 -04:00
100thCoin
d89f9e03e6 Added a test for the DMC Bus Conflict and $4015
The DMC bus conflict reads from address $4015, clearing the frame counter interrupt flag.
2025-06-04 01:38:50 -04:00
100thCoin
d370249903 Added tests for the DMC DMA
Added tests for the DMC DMA.
Fixed the "less reliable" DMC Sync subroutine.
Added a test for DMC DMA bus conflicts.
2025-06-04 01:36:21 -04:00
100thCoin
53fa062bbc Fixed the infinite loop in my backup DMC DMA sync
I guess it needed to be BIT after all.
2025-06-02 12:10:20 -04:00
100thCoin
496952bb2f Added APU tests
Added a test for Length counter timing, and the 4-step / 5-step frame counter behavior.
Updated the unofficial instruction tests to also test for instruction length.
Updated SHA and SHS behavior 1 to print magic numbers.
Cleaned up the clockslides.
Tried to prevent infinite loops due to incorrect DMC DMA timing.
Error codes are erased by PASS.
Sprite evaluation tests now clear the garbage tiles in the overscan area.
DMC DMA + $4016 now also passes with the famicom behavior.
2025-06-01 00:47:31 -04:00
100thCoin
ae4464b296 Fixed a few typos, and re-formatted some whitespaces
I wanted the table in test 4 of APU register activation to look good with different tab lengths.
2025-05-30 15:44:05 -04:00
100thCoin
7aff6231cc Updated the Instruction Timing test
It no longer has an alignment-specific issue.
(I am now running a calibration test just to check for alignment specific differences)
2025-05-30 14:57:59 -04:00
100thCoin
f54d568efe Added a test for Read-Modify-Write $2007
More console verification of this test is needed, but from the tests others have made so far, it seems consistent.
2025-05-30 01:23:06 -04:00
100thCoin
26e1fad16f Added a test for NMI and IRQ overlapping
Added a test for NMI and IRQ overlapping
2025-05-29 18:56:48 -04:00
100thCoin
019dedde22 Added a test for NMI overlapping a BRK instruction
This test has two possible answer keys depending on CPU/PPU clock alignment.
2025-05-29 17:07:39 -04:00
100thCoin
6c87a525dd Updated the Interrupt Flag Latency test.
I now stall for 50 CPU cycles in each test to wait for the IRQ to be ready, even with incorrect DMA timing. I now test for correct timing on test 8.
2025-05-29 15:06:44 -04:00
100thCoin
bd32c9133e Added a test for Interrupt Flag Latency
Added a test for Interrupt Flag Latency, and a huge explanation for why it occurs.
This tests with CLI, SEI, PLP, RTI, and branches.
2025-05-29 14:27:52 -04:00
100thCoin
a8785427ba Added automatic suite testing
Added automatic suite testing by pressing A on the page selector for a suite.
2025-05-27 15:58:33 -04:00
100thCoin
ae51552f27 Added tests for instruction timing
Added tests for instruction timing
2025-05-27 14:18:03 -04:00
100thCoin
18eab5eb2d Added a test for DMA + $4016, and Controller Strobing
Added a test for DMA + $4016, and Controller Strobing
2025-05-25 00:54:51 -04:00
100thCoin
8e3073027d Added a failsafe in the APU Reg Activation test to prevent crashes.
In the specific instance of failure in which you read from controller port 2 too many times with your DMA, you will run an RTS instruction, and error code 4.
2025-05-23 23:19:53 -04:00
100thCoin
4bfa30b5e1 Added a test for APU Register Activation
After a series of checks to make sure you can even try running this test, make the absolute most insane thing ever happen: An OAM DMA while the Program Counter is at address $4000. This requires a lot of moving parts to go exactly right. PPU open bus, the PPU read buffer, Precise DMC DMA timing, the DMC DMA can update the data bus, and proper open bus emulation, leading to a test that confirms the APU registers can be read by the OAM DMA if the 6502 Address bus is pointing to Page $40.
2025-05-23 22:43:20 -04:00
100thCoin
7c4f56c1c9 Added a test for various Address $2004 behavior
Added a test for various Address $2004 behavior:
Writes to $2004 update OAM, and increment the OAM address by 1
Reads from $2004 give you a value in OAM, but do not increment the OAM address
Reads from $2004 during PPU cycle 1 to 64 of a visible scanline (with rendering enabled) will always read $FF
Reads from $2004 during PPU cycle 1 to 64 of a visible scanline (with rendering disabled) does a regular read of $2004
Writing to $2004 on a visible scanline increments the OAM address by 4
Writing to $2004 on a visible scanline doesn't write to OAM
2025-05-23 14:02:09 -04:00
100thCoin
e4ccbe94fc Fixed inconsistencies with the Misaligned OAM test
By timing the write to address $2003 between dots 241 and 261, by prepping the databus before the write cycle to $2003, and by keeping the test inside OAM row 0, the corruption should no longer occur.
2025-05-23 12:36:25 -04:00
100thCoin
160a73f02e Fixed typos in the comments of the Misaligned OAM Behavior test
Fixed typos in the comments of the Misaligned OAM Behavior test
I also spent all day trying to make this test more consistent on console by using $2004 to move the PPUOAMAddress instead of $2003, but then I had to deal with OAM Corruption which was gross and I gave up.
2025-05-22 23:18:13 -04:00
100thCoin
2e5ccaed4e Updated the test for misaligned OAM
Updated the test for misaligned OAM, and added several comments to help explain the test.
2025-05-22 15:49:35 -04:00
100thCoin
77734729c5 Added tests for the sprite overflow flag and Misaligned OAM
Added tests for the sprite overflow flag and a WIP test for Misaligned OAM
2025-05-21 02:53:30 -04:00
100thCoin
2b8c160019 Added comments explaining every helper function
Added comments explaining every helper function
2025-05-20 17:29:46 -04:00
100thCoin
e9fcfcedd9 Fixed the inconsistent behavior of the Arbitrary Sprite Zero test
Or so I assume.
I stall for 2 more CPU cycles now, and I also changed the writes to $2003 to use mirrors corresponding with the OAM value I wish to write. I.E, instead of using OAM address $80 and $81, I use $20 and $21, writing to $2003 and $2103.
2025-05-20 16:42:06 -04:00
100thCoin
76fba6c93f Added a test for Arbitrary Sprite Zero
Added a test for Arbitrary Sprite Zero
2025-05-20 16:23:00 -04:00
100thCoin
901875c2eb Expanded the Sprite Zero Hit test
Added tests for if sprite zero is vertically off screen, masked away by the leftmost 8 pixels, a single dot sprite landing in an open 1x1 pixel window (missing the hit), and a test for "precise" Sprite Zero Hit timing. (within a 2 CPU cycle window)
2025-05-20 13:21:25 -04:00
100thCoin
264db673ff Updated the open bus test
Now when checking the open bus bits of address $4016 and $4017, it also runs a scenario in which the bits wont be $40
2025-05-19 19:21:14 -04:00
100thCoin
63395e439c Added a very basic sprite zero hit test
This checks for various cases when a sprite zero hit should and should not occur.
2025-05-19 18:26:53 -04:00
100thCoin
e701f4c840 Added a test for disabling the NMI at the start of VBlank
Added a test for disabling the NMI at the start of VBlank
2025-05-19 13:31:52 -04:00
100thCoin
1d5f4854ff Added a test for NMI timing at the end of VBlank
Added a test for NMI timing at the end of VBlank
2025-05-19 00:56:14 -04:00
100thCoin
078bf4954b Added a test for NMI Suppression
Added a test for NMI Suppression
2025-05-19 00:23:13 -04:00
100thCoin
e3cec3fcb5 The unofficial instructions exist test now works for both SHA behaviors.
The unofficial instructions exist test now works for both SHA behaviors, and also both SHS behaviors.
2025-05-18 23:17:05 -04:00
100thCoin
5f164483e7 Fixed the Unofficial Instructions exist test
I accidentally broke the SHA and SHS instructions when trying to set X to FF in order to prevent behavior differences from breaking that test. That is now fixed.
2025-05-18 15:33:57 -04:00