I accidentally broke the SHA and SHS instructions when trying to set X to FF in order to prevent behavior differences from breaking that test. That is now fixed.
Added tests for NMI toggle control, and NMI timing
The NMI timing test has a single PPU-cycle of leeway, since my console has 1 CPU/PPU clock alignment where the NMI happens at a different time.
Added the test for VBlank beginning, which tests the $2002 VBlank flag being read during the beginning of VBlank.
Added the test for VBlank end, which tests the timing of the $2002 Vblank flag being disabled at the end of VBlank.
The SHA and SHS tests print the behavior used before running tests. This makes sure you can still see which behavior is used even if an error is encountered.
If your emulator doesn't update the databus during a DMA, there is now a check for that when booting the ROM, so it can choose the best DMA Sync routine.
This new method works regardless of DMA timing inaccuracies, as long as the duration between DMAs is accurate. Therefore, this will now work on many more emulators, and still work on console.
Tests for the SHA, SHS, SHX, and SHY instructions now have an additional test, where a DMA is precisely timed 2 cycles before the write cycle. This changes the behavior of those instructions, which this test now accounts for.
Added the PPU Open Bus Test to the menu
Extended the PPU Open Bus test to check that all PPU registers update the PPU data bus.
Extended the PPU Open Bus test to check that bit 0 through 4 of address $2002 is PPU open bus.
Instead of relying on the double-writes to $2007, which has CPU/PPU click alignment behavior, this relies on double-writes to $2006, which does not,
I pretty much just copied the test by bisqwit and blargg.
I made changes to the stack pointer in a previous commit as a means to prevent a stack pointer value of 00 in a test from overwriting the bottom of the stack. That modified the results of test K, as it expected the stack pointer to have the value F6. My solution was to force the stack pointer to a known value for the test.
The SHA (Indirect), Y test now properly tests for which behavior to use.
If behavior 2 is used, the ROM will now determine the magic value and print it on screen.
The SHA instructions are now known to have two different behaviors. This will not only check if your emulator is running this instruction, but also print which behavior.
Added a test for DMA + $2007 reads
This required making a function to sync the DMA to run on a very specific CPU cycle in a function.
It's pretty much just a copy of what blargg was doing in their DMA timing related tests.
Added tests for all SHA instructions
(Correction, there are more unofficial instructions to test.)
TODO: Per my current understanding, the high byte instability doesn't occur if we time a DMA on the cycle before the write. Include that in the test.
This test isn't finished yet, and only runs a single test for each instruction. Though this commit also includes the entire "engine" for these tests that will be used on all instruction tests.
