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[Core/MS] improved Japanese Master System I/O chip (315-5297) emulation (verified on real hardware by Charles MacDonald)
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@ -4,8 +4,8 @@
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*
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* Support for Master System (315-5216, 315-5237 & 315-5297), Game Gear & Mega Drive I/O chips
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -437,13 +437,6 @@ void io_z80_write(unsigned int offset, unsigned int data, unsigned int cycles)
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/* Send TR/TH state to connected peripherals */
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port[0].data_w((data << 1) & 0x60, (~data << 5) & 0x60);
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port[1].data_w((data >> 1) & 0x60, (~data << 3) & 0x60);
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/* Japanese model specific */
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if (region_code == REGION_JAPAN_NTSC)
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{
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/* Reading TH & TR pins always return 0 when set as output */
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data &= 0x0F;
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}
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/* Check for TH low-to-high transitions on both ports */
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if ((!(io_reg[0x0F] & 0x80) && (data & 0x80)) ||
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@ -453,6 +446,13 @@ void io_z80_write(unsigned int offset, unsigned int data, unsigned int cycles)
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hvc_latch = hctab[cycles % MCYCLES_PER_LINE] | 0x10000;
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}
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/* Japanese model specific */
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if (region_code == REGION_JAPAN_NTSC)
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{
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/* Reading TH & TR pins always return 0 when set as output */
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data &= 0x0F;
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}
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/* Update I/O Control register */
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io_reg[0x0F] = data;
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}
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@ -4,8 +4,8 @@
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*
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* Support for Master System (315-5216, 315-5237 & 315-5297), Game Gear & Mega Drive I/O chips
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -4,8 +4,8 @@
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*
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* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -468,18 +468,43 @@ void z80_ms_port_w(unsigned int port, unsigned char data)
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default:
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{
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/* write FM chip if enabled */
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if (!(port & 4) && (config.ym2413 & 1))
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/* check if YM2413 chip is enabled */
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if (config.ym2413 & 1)
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{
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fm_write(Z80.cycles, port, data);
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/* 315-5297 I/O chip decodes bit 1 to enable/disable PSG output */
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if (region_code == REGION_JAPAN_NTSC)
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{
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io_reg[6] = (data & 2) ? 0xFF : 0x00;
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SN76489_Config(Z80.cycles, config.psg_preamp, config.psgBoostNoise, io_reg[6]);
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/* 315-5297 I/O chip decodes full address range */
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port &= 0xFF;
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/* internal YM2413 chip */
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if ((port == 0xF0) || (port == 0xF1))
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{
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fm_write(Z80.cycles, port, data);
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return;
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}
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/* Audio control register (315-5297 I/O chip specific) */
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if (port == 0xF2)
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{
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/* D1 D0
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-----
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0 0 : enable only PSG output (power-on default)
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0 1 : enable only FM output
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1 0 : disable both PSG & FM output
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1 1 : enable both PSG and FM output
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*/
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SN76489_Config(Z80.cycles, config.psg_preamp, config.psgBoostNoise, ((data + 1) & 0x02) ? 0x00 : 0xFF);
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fm_write(Z80.cycles, 0x02, data);
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io_reg[6] = data;
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return;
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}
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}
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else if (!(port & 4))
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{
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/* external FM board */
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fm_write(Z80.cycles, port, data);
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return;
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}
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return;
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}
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z80_unused_port_w(port & 0xFF, data);
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@ -520,32 +545,54 @@ unsigned char z80_ms_port_r(unsigned int port)
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default:
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{
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uint8 data = 0xFF;
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/* read FM chip if enabled */
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if (!(port & 4) && (config.ym2413 & 1))
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if (region_code == REGION_JAPAN_NTSC)
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{
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data = YM2413Read();
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/* 315-5297 I/O chip decodes full address range */
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if (region_code == REGION_JAPAN_NTSC)
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port &= 0xFF;
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if (port == 0xF2)
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{
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return data;
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/* D7-D5 : C-SYNC counter (not emulated)
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D4-D2 : Always zero
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D1 : Mute control bit 1
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D0 : Mute control bit 0
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*/
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return io_reg[0x06] & 0x03;
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}
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}
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/* read I/O ports if enabled */
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if (!(io_reg[0x0E] & 0x04))
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if ((port == 0xC0) || (port == 0xC1) || (port == 0xDC) || (port == 0xDD))
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{
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/* read I/O ports if enabled */
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if (!(io_reg[0x0E] & 0x04))
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{
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return io_z80_read(port & 1);
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}
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}
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return z80_unused_port_r(port);
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}
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else
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{
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data &= io_z80_read(port & 1);
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}
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uint8 data = 0xFF;
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return data;
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/* read FM board if enabled */
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if (!(port & 4) && (config.ym2413 & 1))
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{
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data = YM2413Read();
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}
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/* read I/O ports if enabled */
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if (!(io_reg[0x0E] & 0x04))
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{
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data &= io_z80_read(port & 1);
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}
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return data;
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}
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}
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}
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}
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/*--------------------------------------------------------------------------*/
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/* Mark III port handlers */
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/*--------------------------------------------------------------------------*/
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@ -4,8 +4,8 @@
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*
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* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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