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[Core/CD] fixed Memory Mode, Timer and Font Color registers byte access at even address (verified on real hardware, cf. Krikzz's mcd-verificator)

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ekeeke 2022-02-25 15:29:18 +01:00
parent 4a899e8262
commit 58accf0689
2 changed files with 13 additions and 4 deletions
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15
core/cd_hw/scd.c
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@ -2,7 +2,7 @@
* Genesis Plus * Genesis Plus
* Mega CD / Sega CD hardware * Mega CD / Sega CD hardware
* *
* Copyright (C) 2012-2021 Eke-Eke (Genesis Plus GX) * Copyright (C) 2012-2022 Eke-Eke (Genesis Plus GX)
* *
* Redistribution and use of this code or any derivative works are permitted * Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met: * provided that the following conditions are met:
@ -798,6 +798,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
} }
case 0x03: /* Memory Mode */ case 0x03: /* Memory Mode */
case 0x02: /* !LDS and !UDS are ignored (verified on real hardware, cf. Krikzz's mcd-verificator) */
{ {
s68k_poll_sync(1<<0x03); s68k_poll_sync(1<<0x03);
@ -952,8 +953,8 @@ static void scd_write_byte(unsigned int address, unsigned int data)
return; return;
} }
case 0x0e: /* SUB-CPU communication flags */ case 0x0f: /* SUB-CPU communication flags */
case 0x0f: /* !LWR is ignored (Space Ace, Dragon's Lair) */ case 0x0e: /* !LDS and !UDS are ignored (verified on real hardware, cf. Krikzz's mcd-verificator, Space Ace, Dragon's Lair) */
{ {
s68k_poll_sync(1<<0x0f); s68k_poll_sync(1<<0x0f);
scd.regs[0x0f>>1].byte.l = data; scd.regs[0x0f>>1].byte.l = data;
@ -961,6 +962,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
} }
case 0x31: /* Timer */ case 0x31: /* Timer */
case 0x30: /* !LDS and !UDS are ignored (verified on real hardware, cf. Krikzz's mcd-verificator) */
{ {
/* reload timer (one timer clock = 384 CPU cycles) */ /* reload timer (one timer clock = 384 CPU cycles) */
scd.timer = data * TIMERS_SCYCLES_RATIO; scd.timer = data * TIMERS_SCYCLES_RATIO;
@ -992,6 +994,13 @@ static void scd_write_byte(unsigned int address, unsigned int data)
return; return;
} }
case 0x4d: /* Font Color */
case 0x4c: /* !LDS and !UDS are ignored (verified on real hardware, cf. Krikzz's mcd-verificator) */
{
scd.regs[0x4c>>1].byte.l = data;
break;
}
default: default:
{ {
/* SUB-CPU communication words */ /* SUB-CPU communication words */

2
core/cd_hw/scd.h
View File

@ -2,7 +2,7 @@
* Genesis Plus * Genesis Plus
* Mega CD / Sega CD hardware * Mega CD / Sega CD hardware
* *
* Copyright (C) 2012-2021 Eke-Eke (Genesis Plus GX) * Copyright (C) 2012-2022 Eke-Eke (Genesis Plus GX)
* *
* Redistribution and use of this code or any derivative works are permitted * Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met: * provided that the following conditions are met: