[Core/VDP] improved FIFO emulation (fixes lockup in Shin Souseiki Ragnacenty (Japan) and other potential lockup when switching between H32 & H40 mode during active display)
This commit is contained in:
ekeeke
parent
8c72ba0d45
commit
6972a5b0d6
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@ -159,6 +159,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
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* improved Mode 5 sprites parsing accuracy (verified on real hardware)
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* improved Mode 5 sprites rendering timings (fixes "Overdrive" demo)
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* improved FIFO timings accuracy (fixes "Overdrive" Demo)
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* improved FIFO emulation (fixes potential lockup when switching between H32 & H40 mode during active display)
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* improved H-Counter accuracy in H32 mode
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* improved VDP status timing accuracy
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* improved HBLANK flag timing accuracy (verified on real hardware by Nemesis)
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@ -334,8 +334,10 @@ void system_frame_gen(int do_skip)
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mcycles_vdp = 0;
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_slots = 0;
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fifo_cycles[0] = 0;
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fifo_cycles[1] = 0;
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fifo_cycles[2] = 0;
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fifo_cycles[3] = 0;
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/* check if display setings have changed during previous frame */
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if (bitmap.viewport.changed & 2)
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@ -420,8 +422,8 @@ void system_frame_gen(int do_skip)
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/* clear DMA Busy, FIFO FULL & field flags */
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status &= 0xFEED;
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/* set VBLANK & FIFO EMPTY flags */
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status |= 0x0208;
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/* set VBLANK flag */
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status |= 0x08;
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/* check interlaced modes */
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if (interlaced)
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@ -675,8 +677,10 @@ void system_frame_scd(int do_skip)
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scd.cycles = 0;
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_slots = 0;
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fifo_cycles[0] = 0;
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fifo_cycles[1] = 0;
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fifo_cycles[2] = 0;
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fifo_cycles[3] = 0;
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/* check if display setings have changed during previous frame */
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if (bitmap.viewport.changed & 2)
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@ -761,8 +765,8 @@ void system_frame_scd(int do_skip)
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/* clear DMA Busy, FIFO FULL & field flags */
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status &= 0xFEED;
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/* set VBLANK & FIFO EMPTY flags */
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status |= 0x0208;
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/* set VBLANK flag */
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status |= 0x08;
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/* check interlaced modes */
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if (interlaced)
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@ -1000,8 +1004,10 @@ void system_frame_sms(int do_skip)
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mcycles_vdp = 0;
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_slots = 0;
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fifo_cycles[0] = 0;
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fifo_cycles[1] = 0;
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fifo_cycles[2] = 0;
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fifo_cycles[3] = 0;
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/* check if display settings has changed during previous frame */
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if (bitmap.viewport.changed & 2)
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186
core/vdp_ctrl.c
186
core/vdp_ctrl.c
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@ -52,6 +52,7 @@
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} \
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bg_name_dirty[name] |= (1 << ((addr >> 2) & 7)); \
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}
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/* VINT timings */
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#define VINT_H32_MCYCLE (770)
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#define VINT_H40_MCYCLE (788)
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@ -98,8 +99,7 @@ uint16 v_counter; /* Vertical counter */
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uint16 vc_max; /* Vertical counter overflow value */
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uint16 lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
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uint16 max_sprite_pixels; /* Max. sprites pixels per line (parsing & rendering) */
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int32 fifo_write_cnt; /* VDP FIFO write count */
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uint32 fifo_slots; /* VDP FIFO access slot count */
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uint32 fifo_cycles[4]; /* VDP FIFO read-out cycles */
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uint32 hvc_latch; /* latched HV counter */
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uint32 vint_cycle; /* VINT occurence cycle */
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const uint8 *hctab; /* pointer to H Counter table */
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@ -123,7 +123,6 @@ static void vdp_z80_data_w_ms(unsigned int data);
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static void vdp_z80_data_w_gg(unsigned int data);
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static void vdp_z80_data_w_sg(unsigned int data);
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static void vdp_bus_w(unsigned int data);
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static void vdp_fifo_update(unsigned int cycles);
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static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles);
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static void vdp_dma_68k_ext(unsigned int length);
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static void vdp_dma_68k_ram(unsigned int length);
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@ -150,7 +149,6 @@ static int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis m
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static uint16 fifo[4]; /* FIFO ring-buffer */
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static int fifo_idx; /* FIFO write index */
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static int fifo_byte_access; /* FIFO byte access flag */
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static uint32 fifo_cycles; /* FIFO next access cycle */
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static int *fifo_timing; /* FIFO slots timing table */
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static int hblank_start_cycle; /* HBLANK flag set cycle */
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static int hblank_end_cycle; /* HBLANK flag clear cycle */
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@ -170,16 +168,20 @@ static const uint16 vc_table[4][2] =
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};
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/* FIFO access slots timings */
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static const int fifo_timing_h32[16+4] =
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static const int fifo_timing_h32[] =
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{
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230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370,
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MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510, MCYCLES_PER_LINE + 810, MCYCLES_PER_LINE + 970,
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MCYCLES_PER_LINE + 1130, MCYCLES_PER_LINE + 1450, MCYCLES_PER_LINE + 1610, MCYCLES_PER_LINE + 1770,
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MCYCLES_PER_LINE + 2090, MCYCLES_PER_LINE + 2250, MCYCLES_PER_LINE + 2410, MCYCLES_PER_LINE + 2730
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};
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static const int fifo_timing_h40[18+4] =
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static const int fifo_timing_h40[] =
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{
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352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380,
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MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820, MCYCLES_PER_LINE + 948, MCYCLES_PER_LINE + 1076,
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MCYCLES_PER_LINE + 1332, MCYCLES_PER_LINE + 1460, MCYCLES_PER_LINE + 1588, MCYCLES_PER_LINE + 1844,
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MCYCLES_PER_LINE + 1972, MCYCLES_PER_LINE + 2100, MCYCLES_PER_LINE + 2356, MCYCLES_PER_LINE + 2484
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};
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/* DMA Timings (number of access slots per line) */
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@ -276,9 +278,6 @@ void vdp_reset(void)
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odd_frame = 0;
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im2_flag = 0;
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interlaced = 0;
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fifo_write_cnt = 0;
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fifo_cycles = 0;
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fifo_slots = 0;
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fifo_idx = 0;
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cached_write = -1;
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fifo_byte_access = 1;
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@ -306,10 +305,10 @@ void vdp_reset(void)
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/* default Window clipping */
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window_clip(0,0);
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/* reset VDP status (FIFO empty flag is set) */
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/* reset VDP status */
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if (system_hw & SYSTEM_MD)
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{
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status = vdp_pal | 0x200;
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status = vdp_pal;
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}
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else
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{
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@ -1194,12 +1193,6 @@ unsigned int vdp_68k_ctrl_r(unsigned int cycles)
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/* Cycle-accurate VDP status read (adjust CPU time with current instruction execution time) */
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cycles += m68k_cycles();
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/* Update FIFO status flags if not empty */
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if (fifo_write_cnt)
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{
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vdp_fifo_update(cycles);
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}
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/* Check if DMA Busy flag is set */
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if (status & 2)
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{
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@ -1220,6 +1213,20 @@ unsigned int vdp_68k_ctrl_r(unsigned int cycles)
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/* Clear SOVR & SCOL flags */
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status &= 0xFF9F;
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/* Check if FIFO last entry read-out cycle has been reached */
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if (cycles >= fifo_cycles[(fifo_idx + 3) & 3])
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{
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/* FIFO is empty */
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temp |= 0x200;
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}
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/* Check if FIFO oldest entry read-out cycle is not yet reached */
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else if (cycles < fifo_cycles[fifo_idx])
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{
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/* FIFO is full */
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temp |= 0x100;
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}
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/* VBLANK flag is set when display is disabled */
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if (!(reg[1] & 0x40))
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{
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@ -1991,13 +1998,6 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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/* Active display width */
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if (r & 0x01)
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{
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/* FIFO access slots timings depend on active width */
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if (fifo_slots)
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{
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/* Synchronize VDP FIFO */
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vdp_fifo_update(cycles);
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}
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if (d & 0x01)
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{
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/* Update display-dependant registers */
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@ -2114,68 +2114,6 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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}
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}
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/*--------------------------------------------------------------------------*/
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/* FIFO emulation (Mega Drive VDP specific) */
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/* ---------------------------------------- */
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/* */
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/* CPU access to VRAM, CRAM & VSRAM is limited during active display: */
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/* H32 mode -> 16 access per line */
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/* H40 mode -> 18 access per line */
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/* */
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/* with fixed access slots timings detailled below. */
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/* */
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/* Each VRAM access is byte wide, so one VRAM write (word) need two slots. */
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/* */
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/*--------------------------------------------------------------------------*/
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static void vdp_fifo_update(unsigned int cycles)
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{
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int fifo_read_cnt, line_slots = 0;
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/* number of access slots up to current line */
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int total_slots = dma_timing[0][reg[12] & 1] * ((v_counter + 1) % lines_per_frame);
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/* number of access slots within current line */
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cycles -= mcycles_vdp;
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while (fifo_timing[line_slots] <= cycles)
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{
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line_slots++;
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}
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/* number of processed FIFO entries since last access (byte access needs two slots to process one FIFO word) */
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fifo_read_cnt = (total_slots + line_slots - fifo_slots) >> fifo_byte_access;
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if (fifo_read_cnt > 0)
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{
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/* process FIFO entries */
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fifo_write_cnt -= fifo_read_cnt;
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/* Clear FIFO full flag */
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status &= 0xFEFF;
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if (fifo_write_cnt <= 0)
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{
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/* No more FIFO entries */
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fifo_write_cnt = 0;
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/* Set FIFO empty flag */
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status |= 0x200;
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/* Reinitialize FIFO access slot counter */
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fifo_slots = total_slots + line_slots;
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}
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else
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{
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/* Update FIFO access slot counter */
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fifo_slots += (fifo_read_cnt << fifo_byte_access);
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}
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}
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/* next FIFO update cycle */
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fifo_cycles = mcycles_vdp + fifo_timing[fifo_slots - total_slots + fifo_byte_access];
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}
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/*--------------------------------------------------------------------------*/
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/* Internal 16-bit data bus access function (Mode 5 only) */
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/*--------------------------------------------------------------------------*/
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@ -2335,29 +2273,31 @@ static void vdp_68k_data_w_m4(unsigned int data)
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/* Restricted VDP writes during active display */
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if (!(status & 8) && (reg[1] & 0x40))
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{
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/* Update VDP FIFO */
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vdp_fifo_update(m68k.cycles);
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int slot = 0;
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/* Clear FIFO empty flag */
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status &= 0xFDFF;
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/* Cycle-accurate VDP data port access */
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int cycles = m68k.cycles;
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/* up to 4 words can be stored */
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if (fifo_write_cnt < 4)
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/* Check against last FIFO entry read-out cycle */
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if (cycles < fifo_cycles[(fifo_idx + 3) & 3])
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{
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/* Increment FIFO counter */
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fifo_write_cnt++;
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/* Check against oldest FIFO entry read-out cycle */
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if (cycles < fifo_cycles[fifo_idx])
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{
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/* FIFO is full, 68k waits until oldest FIFO entry is processed (Chaos Engine / Soldiers of Fortune, Double Clutch, Titan Overdrive Demo) */
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m68k.cycles = (((fifo_cycles[fifo_idx] + 6) / 7) * 7);
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}
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/* Set FIFO full flag if 4 words are stored */
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status |= ((fifo_write_cnt & 4) << 6);
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/* FIFO is not empty, next FIFO entry will be processed after last FIFO entry */
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cycles = fifo_cycles[(fifo_idx + 3) & 3];
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}
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else
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{
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/* CPU is halted until next FIFO entry processing */
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m68k.cycles = fifo_cycles;
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/* Update FIFO access slot counter */
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fifo_slots += (fifo_byte_access + 1);
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}
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/* Determine next FIFO entry processing slot */
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cycles -= mcycles_vdp;
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while (cycles >= fifo_timing[slot]) slot++;
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/* Update last FIFO entry read-out cycle */
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fifo_cycles[fifo_idx] = mcycles_vdp + fifo_timing[slot + fifo_byte_access];
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}
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/* Check destination code */
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@ -2427,31 +2367,33 @@ static void vdp_68k_data_w_m5(unsigned int data)
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/* Restricted VDP writes during active display */
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if (!(status & 8) && (reg[1] & 0x40))
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{
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/* Update VDP FIFO */
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vdp_fifo_update(m68k.cycles);
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int slot = 0;
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/* Clear FIFO empty flag */
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status &= 0xFDFF;
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/* Cycle-accurate VDP data port access */
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int cycles = m68k.cycles;
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/* up to 4 words can be stored */
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if (fifo_write_cnt < 4)
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/* Check against last FIFO entry read-out cycle */
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if (cycles < fifo_cycles[(fifo_idx + 3) & 3])
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{
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/* Increment FIFO counter */
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fifo_write_cnt++;
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/* Check against oldest FIFO entry read-out cycle */
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if (cycles < fifo_cycles[fifo_idx])
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{
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/* FIFO is full, 68k waits until oldest FIFO entry is processed (Chaos Engine / Soldiers of Fortune, Double Clutch, Titan Overdrive Demo) */
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m68k.cycles = (((fifo_cycles[fifo_idx] + 6) / 7) * 7);
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}
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/* Set FIFO full flag if 4 words are stored */
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status |= ((fifo_write_cnt & 4) << 6);
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/* FIFO is not empty, next FIFO entry will be processed after last FIFO entry */
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cycles = fifo_cycles[(fifo_idx + 3) & 3];
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}
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else
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{
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/* CPU is halted until next FIFO entry processing (Chaos Engine / Soldiers of Fortune, Double Clutch, Titan Overdrive Demo) */
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m68k.cycles = fifo_cycles;
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/* Update FIFO access slot counter */
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fifo_slots += (fifo_byte_access + 1);
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}
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/* Determine next FIFO entry processing slot */
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cycles -= mcycles_vdp;
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while (cycles >= fifo_timing[slot]) slot++;
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/* Update last FIFO entry read-out cycle */
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fifo_cycles[fifo_idx] = mcycles_vdp + fifo_timing[slot + fifo_byte_access];
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}
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/* Write data */
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vdp_bus_w(data);
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@ -3193,7 +3135,7 @@ static void vdp_dma_fill(unsigned int length)
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{
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int name;
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/* Get source data from last written FIFO entry */
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/* Get source data from last written FIFO entry */
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uint8 data = fifo[(fifo_idx+3)&3] >> 8;
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do
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@ -78,8 +78,7 @@ extern uint16 vc_max;
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extern uint16 vscroll;
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extern uint16 lines_per_frame;
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extern uint16 max_sprite_pixels;
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extern int32 fifo_write_cnt;
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extern uint32 fifo_slots;
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extern uint32 fifo_cycles[4];
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extern uint32 hvc_latch;
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extern uint32 vint_cycle;
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extern const uint8 *hctab;
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