mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-09-10 16:53:15 +02:00
[Core/VDP] improved accuracy of DMA Copy/Fill & added support for CRAM/VSRAM Fill (verified on real hardware)
This commit is contained in:
EkeEke
twinaphex
parent
16b00f9368
commit
71cf37cb14
274
core/vdp_ctrl.c
274
core/vdp_ctrl.c
@ -133,8 +133,8 @@ static uint16 addr_latch; /* Latched A15, A14 of address */
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static uint16 sat_base_mask; /* Base bits of SAT */
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static uint16 sat_addr_mask; /* Index bits of SAT */
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static uint16 dma_src; /* DMA source address */
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static uint16 dmafill; /* DMA Fill setup */
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static uint32 dma_endCycles; /* 68k cycles to DMA end */
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static int dmafill; /* DMA Fill pending flag */
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static int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
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static uint16 fifo[4]; /* FIFO ring-buffer */
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static int fifo_idx; /* FIFO write index */
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@ -649,7 +649,7 @@ void vdp_dma_update(unsigned int cycles)
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/* Check if DMA is finished */
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if (!dma_length)
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{
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/* DMA source address registers are incremented during DMA */
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/* DMA source address registers are incremented during DMA (even DMA Fill) */
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uint16 end = reg[21] + (reg[22] << 8) + reg[19] + (reg[20] << 8);
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reg[21] = end & 0xff;
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reg[22] = end >> 8;
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@ -730,17 +730,29 @@ void vdp_68k_ctrl_w(unsigned int data)
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{
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case 2:
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{
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/* DMA Fill will be triggered by next DATA port write */
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dmafill = 0x100;
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/* DMA Fill */
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dma_type = 2;
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/* DMA is pending until next DATA port write */
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dmafill = 1;
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/* Set DMA Busy flag */
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status |= 0x02;
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/* DMA end cycle is not initialized yet (this prevents DMA Busy flag from being cleared on VDP status read) */
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dma_endCycles = 0xffffffff;
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break;
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}
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case 3:
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{
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/* DMA Copy */
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dma_type = 3;
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/* DMA length */
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dma_length = (reg[20] << 8) | reg[19];
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/* Zero DMA length */
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/* Zero DMA length (pre-decrementing counter) */
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if (!dma_length)
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{
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dma_length = 0x10000;
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@ -749,18 +761,20 @@ void vdp_68k_ctrl_w(unsigned int data)
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/* DMA source address */
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dma_src = (reg[22] << 8) | reg[21];
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/* trigger DMA copy */
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dma_type = 3;
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/* Trigger DMA */
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vdp_dma_update(m68k.cycles);
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break;
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}
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default:
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{
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/* DMA from 68k bus */
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dma_type = (code & 0x06) ? 0 : 1;
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/* DMA length */
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dma_length = (reg[20] << 8) | reg[19];
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/* Zero DMA length */
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/* Zero DMA length (pre-decrementing counter) */
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if (!dma_length)
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{
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dma_length = 0x10000;
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@ -779,8 +793,7 @@ void vdp_68k_ctrl_w(unsigned int data)
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dma_length--;
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}
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/* trigger DMA from 68k bus */
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dma_type = (code & 0x06) ? 0 : 1;
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/* Trigger DMA */
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vdp_dma_update(m68k.cycles);
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break;
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}
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@ -876,16 +889,25 @@ void vdp_z80_ctrl_w(unsigned int data)
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case 2:
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{
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/* DMA Fill will be triggered by next write to DATA port */
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dmafill = 0x100;
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dmafill = 1;
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/* Set DMA Busy flag */
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status |= 0x02;
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/* DMA end cycle is not initialized yet (this prevents DMA Busy flag from being cleared on VDP status read) */
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dma_endCycles = 0xffffffff;
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break;
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}
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case 3:
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{
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/* DMA copy */
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dma_type = 3;
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/* DMA length */
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dma_length = (reg[20] << 8) | reg[19];
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/* Zero DMA length */
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/* Zero DMA length (pre-decrementing counter) */
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if (!dma_length)
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{
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dma_length = 0x10000;
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@ -894,8 +916,7 @@ void vdp_z80_ctrl_w(unsigned int data)
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/* DMA source address */
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dma_src = (reg[22] << 8) | reg[21];
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/* trigger DMA copy */
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dma_type = 3;
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/* Trigger DMA */
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vdp_dma_update(Z80.cycles);
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break;
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}
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@ -1242,10 +1263,15 @@ unsigned int vdp_68k_ctrl_r(unsigned int cycles)
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vdp_fifo_update(cycles);
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}
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/* Update DMA Busy flag */
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if ((status & 2) && !dma_length && (cycles >= dma_endCycles))
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/* Check if DMA Busy flag is set */
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if (status & 2)
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{
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status &= 0xFFFD;
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/* Check if DMA is finished */
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if (!dma_length && (cycles >= dma_endCycles))
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{
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/* Clear DMA Busy flag */
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status &= 0xFFFD;
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}
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}
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/* Return VDP status */
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@ -1283,10 +1309,15 @@ unsigned int vdp_z80_ctrl_r(unsigned int cycles)
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/* Cycle-accurate SOVR & VINT flags */
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int line = (lines_per_frame + (cycles / MCYCLES_PER_LINE) - 1) % lines_per_frame;
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/* Update DMA Busy flag (Mega Drive VDP specific) */
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if ((system_hw & SYSTEM_MD) && (status & 2) && !dma_length && (cycles >= dma_endCycles))
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/* Check if DMA busy flag is set (Mega Drive VDP specific) */
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if (status & 2)
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{
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status &= 0xFD;
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/* Check if DMA is finished */
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if (!dma_length && (cycles >= dma_endCycles))
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{
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/* Clear DMA Busy flag */
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status &= 0xFD;
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}
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}
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/* Check if we are already on next line */
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@ -1300,7 +1331,7 @@ unsigned int vdp_z80_ctrl_r(unsigned int cycles)
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}
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else if ((line >= 0) && (line < bitmap.viewport.h) && !(work_ram[0x1ffb] & cart.special))
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{
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/* Check sprites overflow & collision */
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/* render next line to check sprites overflow & collision */
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render_line(line);
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}
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}
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@ -2417,23 +2448,22 @@ static void vdp_68k_data_w_m5(unsigned int data)
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/* Write data */
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vdp_bus_w(data);
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/* DMA Fill */
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if (dmafill & 0x100)
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/* Check if DMA Fill is pending */
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if (dmafill)
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{
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/* Fill data = MSB (DMA fill flag is cleared) */
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dmafill = data >> 8;
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/* Clear DMA Fill pending flag */
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dmafill = 0;
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/* DMA length */
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dma_length = (reg[20] << 8) | reg[19];
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/* Zero DMA length */
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/* Zero DMA length (pre-decrementing counter) */
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if (!dma_length)
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{
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dma_length = 0x10000;
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}
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/* Process DMA Fill*/
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dma_type = 2;
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/* Trigger DMA */
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vdp_dma_update(m68k.cycles);
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}
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}
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@ -2694,23 +2724,22 @@ static void vdp_z80_data_w_m5(unsigned int data)
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/* Increment address register */
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addr += reg[15];
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/* DMA Fill */
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if (dmafill & 0x100)
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/* Check if DMA Fill is pending */
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if (dmafill)
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{
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/* Fill data (DMA fill flag is cleared) */
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dmafill = data;
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/* Clear DMA Fill pending flag */
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dmafill = 0;
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/* DMA length */
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dma_length = (reg[20] << 8) | reg[19];
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/* Zero DMA length */
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/* Zero DMA length (pre-decrementing counter) */
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if (!dma_length)
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{
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dma_length = 0x10000;
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}
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/* Process DMA Fill */
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dma_type = 2;
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/* Trigger DMA */
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vdp_dma_update(Z80.cycles);
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}
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}
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@ -3074,11 +3103,11 @@ static void vdp_dma_68k_io(unsigned int length)
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dma_src = (source >> 1) & 0xffff;
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}
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/* VRAM Copy (TODO: check if CRAM or VSRAM copy is possible) */
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/* VRAM Copy */
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static void vdp_dma_copy(unsigned int length)
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{
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/* VRAM read/write operation only */
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if ((code & 0x1E) == 0x10)
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/* CD4 should be set (CD0-CD3 ignored) otherwise VDP locks (hard reset needed) */
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if (code & 0x10)
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{
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int name;
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uint8 data;
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@ -3088,52 +3117,9 @@ static void vdp_dma_copy(unsigned int length)
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do
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{
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/* Read byte from source address */
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data = READ_BYTE(vram, source);
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/* Read byte from adjacent VRAM source address */
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data = READ_BYTE(vram, source ^ 1);
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/* Intercept writes to Sprite Attribute Table */
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if ((addr & sat_base_mask) == satb)
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{
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/* Update internal SAT */
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WRITE_BYTE(sat, addr & sat_addr_mask, data);
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}
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/* Write byte to VRAM address */
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WRITE_BYTE(vram, addr, data);
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/* Update pattern cache */
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MARK_BG_DIRTY(addr);
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/* Increment source address */
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source++;
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/* Increment VRAM address */
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addr += reg[15];
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}
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while (--length);
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/* Update DMA source address */
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dma_src = source;
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}
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else
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{
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/* DMA source & VRAM addresses are still incremented */
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addr += reg[15] * length;
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dma_src += length;
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}
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}
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/* VRAM Fill (TODO: check if CRAM or VSRAM fill is possible) */
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static void vdp_dma_fill(unsigned int length)
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{
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/* VRAM write operation only (Williams Greatest Hits after soft reset) */
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if ((code & 0x1F) == 0x01)
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{
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int name;
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uint8 data = dmafill;
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do
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{
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/* Intercept writes to Sprite Attribute Table */
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if ((addr & sat_base_mask) == satb)
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{
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@ -3141,20 +3127,126 @@ static void vdp_dma_fill(unsigned int length)
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WRITE_BYTE(sat, (addr & sat_addr_mask) ^ 1, data);
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}
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/* Write byte to adjacent VRAM address */
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/* Write byte to adjacent VRAM destination address */
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WRITE_BYTE(vram, addr ^ 1, data);
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/* Update pattern cache */
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MARK_BG_DIRTY (addr);
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MARK_BG_DIRTY(addr);
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/* Increment VRAM address */
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/* Increment VRAM source address */
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source++;
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/* Increment VRAM destination address */
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addr += reg[15];
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}
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while (--length);
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}
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else
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{
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/* VRAM address is still incremented */
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addr += reg[15] * length;
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/* Update DMA source address */
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dma_src = source;
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}
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}
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/* DMA Fill */
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static void vdp_dma_fill(unsigned int length)
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{
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/* Check destination code (CD0-CD3) */
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switch (code & 0x0F)
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{
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case 0x01: /* VRAM */
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{
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int name;
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/* Get source data from last written FIFO entry */
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uint8 data = fifo[(fifo_idx+3)&3] >> 8;
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do
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{
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/* Intercept writes to Sprite Attribute Table */
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if ((addr & sat_base_mask) == satb)
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{
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/* Update internal SAT */
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WRITE_BYTE(sat, (addr & sat_addr_mask) ^ 1, data);
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}
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/* Write byte to adjacent VRAM address */
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WRITE_BYTE(vram, addr ^ 1, data);
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/* Update pattern cache */
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MARK_BG_DIRTY (addr);
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/* Increment VRAM address */
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addr += reg[15];
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}
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while (--length);
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break;
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}
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case 0x03: /* CRAM */
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{
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/* Get source data from next available FIFO entry */
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uint16 data = fifo[fifo_idx];
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/* Pack 16-bit bus data (BBB0GGG0RRR0) to 9-bit CRAM data (BBBGGGRRR) */
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data = ((data & 0xE00) >> 3) | ((data & 0x0E0) >> 2) | ((data & 0x00E) >> 1);
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do
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{
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/* Pointer to CRAM 9-bit word */
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uint16 *p = (uint16 *)&cram[addr & 0x7E];
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/* Check if CRAM data is being modified */
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if (data != *p)
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{
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/* CRAM index (64 words) */
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int index = (addr >> 1) & 0x3F;
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/* Write CRAM data */
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*p = data;
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/* Color entry 0 of each palette is never displayed (transparent pixel) */
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if (index & 0x0F)
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{
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/* Update color palette */
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color_update_m5(index, data);
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}
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/* Update backdrop color */
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if (index == border)
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{
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color_update_m5(0x00, data);
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}
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}
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/* Increment CRAM address */
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addr += reg[15];
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}
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while (--length);
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break;
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}
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case 0x05: /* VSRAM */
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{
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/* Get source data from next available FIFO entry */
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uint16 data = fifo[fifo_idx];
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do
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{
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/* Write VSRAM data */
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*(uint16 *)&vsram[addr & 0x7E] = data;
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/* Increment VSRAM address */
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addr += reg[15];
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}
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while (--length);
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break;
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}
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default:
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{
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/* invalid destination does nothing (Williams Greatest Hits after soft reset) */
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/* address is still incremented */
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addr += reg[15] * length;
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}
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}
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}
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