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[Core/MCD] added CDC & GFX register polling detection / synchronization

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This commit is contained in:
EkeEke 2013-10-21 00:14:44 +02:00 committed by twinaphex
parent a43bad325c
commit f7fc3382fc
3 changed files with 41 additions and 1 deletions
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15
core/cd_hw/cdc.c
View File

@ -214,9 +214,22 @@ void cdc_dma_update(void)
}
}
/* clear DSR bit & set EDT bit (SCD register $04) */
/* clear DSR bit & set EDT bit (CD register $04) */
scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
/* SUB-CPU idle on register $04 polling ? */
if (s68k.stopped & (1<<0x04))
{
/* sync SUB-CPU with CDC */
s68k.cycles = scd.cycles;
/* restart SUB-CPU */
s68k.stopped = 0;
#ifdef LOG_SCD
error("s68k started from %d cycles\n", s68k.cycles);
#endif
}
/* disable DMA transfer */
cdc.dma_w = 0;
}

13
core/cd_hw/gfx.c
View File

@ -692,6 +692,19 @@ void gfx_update(int cycles)
/* end of graphics operation */
scd.regs[0x58>>1].byte.h = 0;
/* SUB-CPU idle on register $58 polling ? */
if (s68k.stopped & (1<<0x08))
{
/* sync SUB-CPU with GFX chip */
s68k.cycles = scd.cycles;
/* restart SUB-CPU */
s68k.stopped = 0;
#ifdef LOG_SCD
error("s68k started from %d cycles\n", s68k.cycles);
#endif
}
/* level 1 interrupt enabled ? */
if (scd.regs[0x32>>1].byte.l & 0x02)
{

14
core/cd_hw/scd.c
View File

@ -287,6 +287,20 @@ static unsigned int scd_read_byte(unsigned int address)
return scd.regs[0x0e>>1].byte.h;
}
/* CDC transfer status */
if (address == 0xff8004)
{
s68k_poll_detect(1<<0x04);
return scd.regs[0x04>>1].byte.h;
}
/* GFX operation status */
if (address == 0xff8058)
{
s68k_poll_detect(1<<0x08);
return scd.regs[0x58>>1].byte.h;
}
/* CDC register data (controlled by BIOS, byte access only ?) */
if (address == 0xff8007)
{