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https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-04 18:05:06 +01:00
[Core/MCD] added CDC & GFX register polling detection / synchronization
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@ -214,9 +214,22 @@ void cdc_dma_update(void)
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}
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/* clear DSR bit & set EDT bit (SCD register $04) */
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/* clear DSR bit & set EDT bit (CD register $04) */
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scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
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scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
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/* SUB-CPU idle on register $04 polling ? */
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if (s68k.stopped & (1<<0x04))
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{
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/* sync SUB-CPU with CDC */
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s68k.cycles = scd.cycles;
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/* restart SUB-CPU */
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s68k.stopped = 0;
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#ifdef LOG_SCD
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error("s68k started from %d cycles\n", s68k.cycles);
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#endif
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}
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/* disable DMA transfer */
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/* disable DMA transfer */
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cdc.dma_w = 0;
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cdc.dma_w = 0;
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}
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}
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@ -692,6 +692,19 @@ void gfx_update(int cycles)
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/* end of graphics operation */
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/* end of graphics operation */
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scd.regs[0x58>>1].byte.h = 0;
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scd.regs[0x58>>1].byte.h = 0;
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/* SUB-CPU idle on register $58 polling ? */
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if (s68k.stopped & (1<<0x08))
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{
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/* sync SUB-CPU with GFX chip */
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s68k.cycles = scd.cycles;
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/* restart SUB-CPU */
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s68k.stopped = 0;
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#ifdef LOG_SCD
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error("s68k started from %d cycles\n", s68k.cycles);
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#endif
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}
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/* level 1 interrupt enabled ? */
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/* level 1 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x02)
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if (scd.regs[0x32>>1].byte.l & 0x02)
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{
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{
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@ -287,6 +287,20 @@ static unsigned int scd_read_byte(unsigned int address)
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return scd.regs[0x0e>>1].byte.h;
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return scd.regs[0x0e>>1].byte.h;
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}
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}
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/* CDC transfer status */
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if (address == 0xff8004)
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{
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s68k_poll_detect(1<<0x04);
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return scd.regs[0x04>>1].byte.h;
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}
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/* GFX operation status */
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if (address == 0xff8058)
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{
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s68k_poll_detect(1<<0x08);
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return scd.regs[0x58>>1].byte.h;
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}
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/* CDC register data (controlled by BIOS, byte access only ?) */
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/* CDC register data (controlled by BIOS, byte access only ?) */
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if (address == 0xff8007)
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if (address == 0xff8007)
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{
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{
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