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https://github.com/ekeeke/Genesis-Plus-GX.git
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------ * improved 68k accuracy (initial reset timing + auto-vectored interrupts handling). * modified Z80 & 68k cores to directly use external cycle count instead of intermediate counters. * improved Z80 & 68k cpu execution/synchronization accuracy, now use Master Clock as common clock reference. * improved PSG & FM chips synchronization with CPU execution (fixed point precision). * completely rewrote sound output processing & mixing: sound chips are now clocked with exact output frame rate to ensure 100% smooth video & audio playback, with no lag or skipping, while still rendering an accurate number of samples per frame. This will also make fast-forward implementation (video AND sound) more trivial. * improved color accuracy in VDP highlight mode to match results observed on real hardware. * improved sprites processing timing accuracy: fixes (un)masked sprites in Mickey Mania (3D level), Sonic 2 (VS mode). * improved horizontal blanking & HINT/VINT occurrence timing accuracy, as measured on real hardware. * improved H-Counter accuracy in 40-cell mode, as measured on real hardware. * optimized Z80 bus status signals * usual code cleanup [GCN/WII] --------- fixed ASNDLIB exit when returning to game fixed audio/video startup sync modified audio back-end engine according to new audio processing core (see above)
236 lines
7.0 KiB
C
236 lines
7.0 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Genesis internals & Bus controller
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Eke-Eke (2007,2008,2009), additional code & fixes for the GCN/Wii port
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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****************************************************************************************/
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#include "shared.h"
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uint8 bios_rom[0x10000]; /* OS ROM */
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uint8 work_ram[0x10000]; /* 68K RAM */
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uint8 zram[0x2000]; /* Z80 RAM */
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uint32 zirq; /* /IRQ to Z80 */
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uint32 zstate; /* Z80 bus state (d0 = BUSACK, d1 = /RESET) */
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uint32 zbank; /* Z80 bank window address */
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uint32 gen_running; /* 0: cpu are in locked state */
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int32 resetline; /* soft reset is triggered on a random line (X-Men 2, Eternal Champions) */
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void set_softreset(void)
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{
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resetline = (int) ((double) (lines_per_frame - 1) * rand() / (RAND_MAX + 1.0));
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}
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void gen_init(void)
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{
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int i;
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/* initialize CPUs */
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m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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m68k_init();
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z80_init(0,0,0,z80_irq_callback);
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/* initialize 68k mapped memory */
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/* $000000-$7fffff is affected to cartridge area (see cart_hw.c) */
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/* $800000-$ffffff is affected to WRAM (see VDP DMA) */
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for (i=0x80; i<0x100; i++)
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{
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m68k_memory_map[i].base = work_ram;
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m68k_memory_map[i].read8 = NULL;
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m68k_memory_map[i].read16 = NULL;
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m68k_memory_map[i].write8 = NULL;
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m68k_memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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/* initialize 68k memory handlers */
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for (i=0x80; i<0xe0; i++)
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{
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/* illegal area */
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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/* Z80 bus */
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m68k_memory_map[0xa0].read8 = z80_read_byte;
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m68k_memory_map[0xa0].read16 = z80_read_word;
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m68k_memory_map[0xa0].write8 = z80_write_byte;
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m68k_memory_map[0xa0].write16 = z80_write_word;
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zbank_memory_map[0xa0].read = zbank_lockup_r;
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zbank_memory_map[0xa0].write = zbank_lockup_w;
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/* I/O & Control registers */
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m68k_memory_map[0xa1].read8 = ctrl_io_read_byte;
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m68k_memory_map[0xa1].read16 = ctrl_io_read_word;
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m68k_memory_map[0xa1].write8 = ctrl_io_write_byte;
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m68k_memory_map[0xa1].write16 = ctrl_io_write_word;
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zbank_memory_map[0xa1].read = zbank_read_ctrl_io;
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zbank_memory_map[0xa1].write = zbank_write_ctrl_io;
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/* SEGA PICO */
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if (system_hw == SYSTEM_PICO)
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{
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m68k_memory_map[0x80].read8 = pico_read_byte;
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m68k_memory_map[0x80].read16 = pico_read_word;
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m68k_memory_map[0x80].write8 = m68k_unused_8_w;
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m68k_memory_map[0x80].write16 = m68k_unused_16_w;
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/* there is no I/O area (Notaz) */
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m68k_memory_map[0xa0].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa0].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa0].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa0].write16 = m68k_unused_16_w;
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m68k_memory_map[0xa1].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa1].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa1].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa1].write16 = m68k_unused_16_w;
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}
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/* VDP */
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = vdp_read_byte;
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m68k_memory_map[i].read16 = vdp_read_word;
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m68k_memory_map[i].write8 = vdp_write_byte;
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m68k_memory_map[i].write16 = vdp_write_word;
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zbank_memory_map[i].read = zbank_read_vdp;
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zbank_memory_map[i].write = zbank_write_vdp;
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}
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}
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void gen_reset(uint32 hard_reset)
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{
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if (hard_reset)
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{
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/* Clear RAM */
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memset (work_ram, 0x00, sizeof (work_ram));
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memset (zram, 0x00, sizeof (zram));
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/* TMSS BIOS support */
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if (config.bios_enabled == 3)
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m68k_memory_map[0].base = bios_rom;
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/* Reset CPU cycle counts */
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mcycles_68k = 0;
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mcycles_z80 = 0;
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}
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zstate = 0; /* Z80 is reset & has control of the bus */
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zirq = 0; /* No interrupts occuring */
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zbank = 0; /* Assume default bank is $000000-$007FFF */
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/* Reset CPUs */
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resetline = -1;
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gen_running = 1;
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m68k_pulse_reset();
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z80_reset();
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}
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void gen_shutdown(void)
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{
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z80_exit();
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}
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/*-----------------------------------------------------------------------
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Bus controller chip functions
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-----------------------------------------------------------------------*/
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void gen_busreq_w(uint32 state)
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{
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if (state)
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{
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/* Bus requested */
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if (zstate == 1)
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{
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/* Z80 is stopped */
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/* Z80 was ON during the last 68k cycles */
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z80_run(mcycles_68k);
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}
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/* update Z80 bus status */
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zstate |= 2;
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}
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else
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{
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/* Bus released */
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if (zstate == 3)
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{
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/* Z80 is restarted */
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/* Z80 was OFF during the last 68k cycles */
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mcycles_z80 = mcycles_68k;
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}
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/* update Z80 bus status */
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zstate &= 1;
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}
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}
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void gen_reset_w(uint32 state)
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{
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if (state)
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{
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/* stop RESET process */
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if (!zstate)
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{
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/* Z80 is restarted */
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/* Z80 was OFF during the last cycles */
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mcycles_z80 = mcycles_68k;
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}
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/* update Z80 bus status */
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zstate |= 1;
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}
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else
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{
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/* start RESET process */
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if (zstate == 1)
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{
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/* Z80 stopped */
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/* z80 was ON during the last 68k cycles */
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z80_run(mcycles_68k);
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}
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/* Reset Z80 & YM2612 */
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z80_reset();
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fm_reset();
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/* update Z80 bus status */
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zstate &= 2;
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}
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}
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void gen_bank_w (uint32 state)
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{
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zbank = ((zbank >> 1) | ((state & 1) << 23)) & 0xFF8000;
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}
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int z80_irq_callback (int param)
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{
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zirq = 0;
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z80_set_irq_line (0, CLEAR_LINE);
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return 0xFF;
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}
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