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https://github.com/Polprzewodnikowy/SummerCart64.git
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99 lines
3.1 KiB
Markdown
99 lines
3.1 KiB
Markdown
# SummerCart64 Firmware
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A FPGA firmware written in Verilog for SummerCart64.
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# Technical Reference Manual
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## Bus peripheral addresses
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- **`0x1000 0000 - 0x13FF FFFF`** - [R/W] *SDRAM Memory*
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- **`0x1D00 0000 - 0x1D00 07FF`** - [R/W] *EEPROM Memory*
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- **`0x1E00 0000 - 0x1E00 0007`** - [R/W] *Cart Registers*
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## Memory spaces
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### SDRAM Memory
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Base address: **`0x1000 0000`**\
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Length: **`64 MB`**\
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Access: Read or Write, 2 byte (16 bit) aligned
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64 MB of SDRAM memory. Available on the bus when **SDRAM** bit in **CART->CR** register is set. Used as ROM storage.
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### EEPROM Memory
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Base address: **`0x1D00 0000`**\
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Length: **`2 kB`**\
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Access: Read or Write, 4 byte (32 bit) aligned
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2 kB of EEPROM Memory. Available on the bus when **EEPROM_PI** bit in **CART->CR** register is set. Used to upload/download EEPROM contents to/from PC.
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## Registers
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### Cart (**CART**) registers
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Base address: **`0x1E00 0000`**
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#### Configuration register (**CR**)
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Address offset: **`0x00`**\
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Powerup value: **`0b0000 0000`**\
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Soft reset value: **`0b00xx x000`**\
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Access: Read or write, 4 byte (32 bit) aligned
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This register is used to enable or disable various modules available on the cart.
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31:5 | 4 | 3 | 2 | 1 | 0
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------|------------|-----------|---|----------|---
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0 | EEPROM_16K | EEPROM_EN | 0 | SDRAM_EN | 0
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x | R/W | R/W | x | R/W | x
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- Bits 31:5: Reserved. Reads as 0, writes are ignored but it's recommended to be set as 0 for future compatibility.
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- Bit 4 **EEPROM_16K**: Sets ID returned by EEPROM to identify itself as 4k or 16k variant.
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- 0: EEPROM 4k variant
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- 1: EEPROM 16k variant
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- Bit 3 **EEPROM_EN**: Enable EEPROM access through SI bus.
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- 0: EEPROM SI access disabled
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- 1: EEPROM SI access enabled
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- Bit 2: Reserved. Reads as 0, writes are ignored but it's recommended to be set as 0 for future compatibility.
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- Bit 1 **SDRAM_EN**: Enable SDRAM access at address base **`0x1000 0000`**. When disabled bootloader flash image is mapped at this address. Cleared by hardware on N64 Reset/NMI event.
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- 0: SDRAM disabled
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- 1: SDRAM enabled
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- Bit 0: Reserved. Reads as 0, writes are ignored but it's recommended to be set as 0 for future compatibility.
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- 0: Flash disabled
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- 1: Flash enabled
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#### CIC and TV type override register (**CIC_TV**)
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Address offset: **`0x04`**\
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Powerup value: **`0x0000 0000`**\
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Access: Read or write, 4 byte (32 bit) aligned
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This register is used for PC -> bootloader communication.
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31:6 | 5:4 | 3:0
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--------|---------|----------
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SWITCH | TV_TYPE | CIC_TYPE
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R/W | R/W | R/W
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- Bits 31:6 **SWITCH**: Additional bits that can be passed to bootloader, currently unused.
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- Bits 5:4 **TV_TYPE**: Overrides TV type in bootloader. Used only when **CIC_TYPE** value is valid (values 1 - 7).
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- 0: PAL TV type
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- 1: NTSC TV type
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- 2: MPAL TV type
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- 3: No TV type override - use TV type provided by ROM header
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- Bits 3:0 **CIC_TYPE**: Overrides CIC type in bootloader.
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- 0: No CIC type override - use CIC type determined from ROM bootcode
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- 1: CIC 5101
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- 2: CIC 6101/7102
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- 3: CIC 6102/7101
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- 4: CIC X103
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- 5: CIC X105
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- 6: CIC X106
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- 7: CIC 8303
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- 8 - 15: Same effect as value 0
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