Mateusz Faderewski 8fd12e9d1a Merge branch 'main' into new-irq

2024-07-21 23:11:52 +02:00

..

fifo

[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)

2024-07-21 11:15:08 +02:00

mcu

[SC64][SW] Implement new libftdi backend in the sc64deployer (#72)

2024-07-21 10:48:20 +02:00

memory

[SC64][FW][SW] Slightly speed up DMA write transfer speed + USB speed test fixes

2024-07-21 22:15:06 +02:00

n64

register PI reg bus

2024-06-12 02:21:13 +02:00

sd

[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)

2024-07-21 11:15:08 +02:00

serv

[SC64][FW][SW] Moved CIC emulation from MCU to FPGA (#56)

2023-12-14 19:26:54 +01:00

usb

[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)

2024-07-21 11:15:08 +02:00

vendor

[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)

2024-07-21 11:15:08 +02:00

top.sv

[SC64][FW] Added placeholder test point outputs in the FPGA project

2024-05-03 17:55:40 +02:00