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Add AES and SHA-1 to AHB stuff, move cache ops to crypto.c
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parent
689f718c64
commit
287248e77c
4
boot2.c
4
boot2.c
@ -62,9 +62,7 @@ void boot2_init() {
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aes_set_iv(iv);
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aes_set_key(otp.common_key);
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memcpy(key, tikptr+0x1bf, 16);
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dc_flushrange(key, 32);
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aes_decrypt(key, key, 1, 0);
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dc_invalidaterange(key, 32);
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memcpy(&datalen, tmdptr+0x1e4+8+4, 4);
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memset(iv, 0, 16);
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@ -73,9 +71,7 @@ void boot2_init() {
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aes_reset();
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aes_set_iv(iv);
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aes_set_key(key);
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dc_flushrange(cntptr, ALIGN_FORWARD(datalen, 16));
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aes_decrypt(cntptr, cntptr, ALIGN_FORWARD(datalen, 16)/16, 0);
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dc_invalidaterange(cntptr, ALIGN_FORWARD(datalen, 16));
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memcpy(boot2, cntptr, datalen);
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boot2_initialized = 1;
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13
crypto.c
13
crypto.c
@ -112,10 +112,17 @@ void aes_decrypt(u8 *src, u8 *dst, u32 blocks, u8 keep_iv)
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this_blocks = blocks;
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if (this_blocks > 0x80)
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this_blocks = 0x80;
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write32(AES_SRC, dma_addr(src));
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write32(AES_DEST, dma_addr(dst));
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dc_flushrange(src, blocks * 16);
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dc_invalidaterange(src, blocks * 16);
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ahb_flush_to(AHB_AES);
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aes_command(AES_CMD_DECRYPT, keep_iv, this_blocks);
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ahb_flush_from(AHB_AES);
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ahb_flush_to(AHB_STARLET);
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blocks -= this_blocks;
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src += this_blocks<<4;
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@ -138,12 +145,8 @@ void aes_ipc(volatile ipc_request *req)
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aes_set_key((u8 *)req->args);
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break;
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case IPC_AES_DECRYPT:
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dc_invalidaterange((u8 *)req->args[0],
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(req->args[3]+1)*16);
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aes_decrypt((u8 *)req->args[0], (u8 *)req->args[1],
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req->args[2], req->args[3]);
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dc_flushrange((u8 *)req->args[1],
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(req->args[3]+1)*16);
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break;
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default:
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gecko_printf("IPC: unknown SLOW AES request %04x\n",
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10
memory.c
10
memory.c
@ -69,8 +69,8 @@ void _ahb_flush_to(enum AHBDEV dev) {
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case AHB_1: mask = 0x4000; break;
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//case 2: mask = 0x0001; break;
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case AHB_NAND: mask = 0x0002; break;
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//case 4: mask = 0x0004; break;
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//case 5: mask = 0x0008; break;
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case AHB_AES: mask = 0x0004; break;
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case AHB_SHA1: mask = 0x0008; break;
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//case 6: mask = 0x0010; break;
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//case 7: mask = 0x0020; break;
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//case 8: mask = 0x0040; break;
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@ -88,6 +88,8 @@ void _ahb_flush_to(enum AHBDEV dev) {
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switch(dev) {
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// 2 to 10 in IOS, add more
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case AHB_NAND:
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case AHB_AES:
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case AHB_SHA1:
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case AHB_SDHC:
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while((read32(HW_18C) & 0xF) == 9)
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set32(HW_188, 0x10000);
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@ -155,6 +157,10 @@ void ahb_flush_from(enum AHBDEV dev)
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case AHB_1:
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req = 1;
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break;
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case AHB_AES:
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case AHB_SHA1:
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req = 2;
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break;
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case AHB_NAND:
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case AHB_SDHC:
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req = 8;
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6
memory.h
6
memory.h
@ -10,9 +10,11 @@
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((typeof(x))(((u32)(x)) & (~(align-1))))
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enum AHBDEV {
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AHB_STARLET = 0, //or MEM2??
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AHB_1 = 1, //or MEM1??
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AHB_STARLET = 0, //or MEM2 or some controller or bus or ??
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AHB_1 = 1, //ppc or something else???
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AHB_NAND = 3,
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AHB_AES = 4,
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AHB_SHA1 = 5,
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AHB_SDHC = 9,
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};
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