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1,560 Commits 5 Branches 35 Tags
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Commit Graph

469 Commits

Author SHA1 Message Date
RedGuyyyy
a2dc303ffc Checkpoint. 2018-03-03 13:41:37 -08:00
RedGuyyyy
208da99184 Checkpoint. 2018-03-03 11:46:32 -08:00
RedGuyyyy
36b7888ee8 Checkpoint. 2018-03-03 08:30:29 -08:00
RedGuyyyy
e1860d40dd Checkpoint. 2018-03-03 06:42:41 -08:00
RedGuyyyy
d121f2cacd Checkpoint. 2018-03-02 17:27:42 -08:00
RedGuyyyy
e797cd0590 Checkpoint. 2018-03-02 16:45:02 -08:00
RedGuyyyy
8d87dfadba Checkpoint. 2018-03-02 14:58:19 -08:00
RedGuyyyy
2d5a45d808 Checkpoint. 2018-03-02 12:17:07 -08:00
RedGuyyyy
975ac00327 Checkpoint. 2018-03-01 20:45:30 -08:00
RedGuyyyy
8fe41987e5 Checkpoint. 2018-02-25 17:27:23 -08:00
RedGuyyyy
d435690e9e Checkpoint. 2018-02-25 14:30:57 -08:00
RedGuyyyy
aac35eda5c Checkpoint. 2018-02-24 20:27:30 -08:00
RedGuyyyy
db09a40a51 Checkpoint. 2018-02-24 19:32:53 -08:00
RedGuyyyy
21aafcc6ff Checkpoint. 2018-02-24 19:15:06 -08:00
RedGuyyyy
e640e46b27 Checkpoint. 2018-02-24 15:51:29 -08:00
RedGuyyyy
362489c1a1 Checkpoint. 2018-02-24 14:15:08 -08:00
RedGuyyyy
4ee373ee71 Checkpoint. 2018-02-24 12:04:31 -08:00
RedGuyyyy
e8739b29cd Checkpoint. 2018-02-24 07:31:35 -08:00
RedGuyyyy
8464017a97 Added initial files. 2018-02-24 07:18:04 -08:00
Maximilian Rehkopf
f29b116417 Update ISE project files again 2017-05-01 09:29:42 +02:00
Maximilian Rehkopf
81efb6f631 Merge branch 'develop' of ssh://github.com/mrehkopf/sd2snes into develop 2017-05-01 09:28:13 +02:00
ikari
7de6107b51 Update ISE project files 2017-04-30 23:38:44 +02:00
ikari
de174c1a15 Add missing change for eda3909 2017-04-30 23:38:21 +02:00
ikari
71c2824ccd MCU command interface: Some state simplifications 2017-04-30 23:36:30 +02:00
ikari
ff8b0a5863 Fix SD clock glitch on FPGA->MCU handoff after partial DMA 2017-04-30 23:30:26 +02:00
ikari
e07b6e2508 MSU1: avoid unaligned SD reads (FPGA side) 2017-04-30 23:29:23 +02:00
ikari
eda39099e4 Extend mode 20 ("LoROM") SRAM mapping 
Banks fe-ff were incorrectly omitted
 2017-04-30 23:21:24 +02:00
Maximilian Rehkopf
8a72bfe122 FPGA: Some bus timing tweaks 
Do not yield too early on cycle end
 2017-04-29 09:30:34 +02:00
ikari
5f72758c7b Fix DAC timing for Rev.E,F,H 
Previous fix for Rev.G broke timing for all other revisions resulting in
nasty distortion. Hopefully still works with all Rev.Gs ;)
 2017-03-10 00:30:21 +01:00
Maximilian Rehkopf
0aace5bfce Tweak Cx4 "normal" speed timing a bit 
Of course this is still off until the revised Cx4 core with the reverse
engineered timings is done, the core was slowed down a bit too much with
0.1.7c though.
 2016-09-28 17:49:18 +02:00
Maximilian Rehkopf
21e6bd9f8a Properly name ROMSEL signal, filter like other control signals 2016-09-28 17:46:09 +02:00
Maximilian Rehkopf
b48b04a03a Inhibit "blind" hook area writes unless unlocked 
Magic value writes are no longer necessary for unlocking
 2016-09-28 16:15:20 +02:00
Maximilian Rehkopf
2a1a539f77 Revert to previous I2S timing for DAC (hopefully helps with Rev.G issues) 2016-09-27 17:46:06 +02:00
Maximilian Rehkopf
1b72a33b34 Relax timing constraint a little bit 2016-09-27 14:15:07 +02:00
Maximilian Rehkopf
d3d7076161 Unlock hook area only on reads of actually enabled vectors 2016-09-27 14:05:21 +02:00
Maximilian Rehkopf
0aadc0cff1 Reset hook must only be unlockable right after system reset 2016-09-27 14:02:12 +02:00
Maximilian Rehkopf
15817c1424 Discard trailing whitespaces 2016-09-27 13:59:51 +02:00
Maximilian Rehkopf
cc280a00cb Fix BS-X PSRAM mapping (WRAM writes corrupt PSRAM) 2016-09-27 13:59:15 +02:00
ikari
43d53557af Another in-game hook overhaul 
- Offload any flow control to FPGA to shave off some more CPU cycles
- Blank screen on reset to menu to avoid graphical artifacts
 2016-09-14 01:39:59 +02:00
ikari
7ace919689 FPGA: apply recent changes to bootstrap config 2016-09-14 01:34:45 +02:00
ikari
76eea82763 FPGA: adjust leftover timing values for 96MHz 2016-09-14 01:33:54 +02:00
ikari
6b06fce13f FPGA: update project settings 2016-08-16 04:01:57 +02:00
ikari
44df05e2c9 Cx4: make multiplier multicycle 
Also it doesn't seem to set any flags. This change relaxes place and
route a bit.
 2016-08-16 04:01:45 +02:00
ikari
20cdeab5a0 Cx4: run at actual 80MHz (20MHz effective) instead of 86MHz 2016-08-16 04:00:26 +02:00
ikari
8d4fe3d4db Back to 96MHz CPU clock 2016-08-16 03:59:24 +02:00
ikari
77520bf30b Revised in-game hook (FPGA side) 
Significant improvements on the hook's CPU footprint and "stealthiness".

* implicit unlocking by FPGA (and by mapper ID for menu operation)
* automatic return vector filling by FPGA, no more duplicate hooks
* do not perform manual read when manual read in progress by game
* map button combination -> command using FPGA (no costly loop in hook)
* reset hook support
 2016-08-16 03:57:15 +02:00
ikari
ef13324d36 Remove obsolete OBC1 enable flag (resolve #73) 2016-04-24 01:50:20 +02:00
ikari
b136c13a02 Discard superfluous registers in DAC interpolation filter 2016-04-24 01:49:05 +02:00
ikari
4ee41ec20c rework external DAC control (play+reset) 2016-04-24 01:48:26 +02:00
ikari
829953b034 DAC: improve audio quality (nearest neighbor -> CIC filter), fix playback rate 2016-04-01 02:00:29 +02:00