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469 Commits

Author SHA1 Message Date
Maximilian Rehkopf
d281b010ba FPGA: fix MSB truncation of MSU status 2016-02-23 00:51:41 +01:00
borti4938
3a986c46a9 Xilinx project files: update timestamps 2016-02-12 09:09:05 +01:00
borti4938
d846b0b908 Merge branch 'develop' of https://github.com/mrehkopf/sd2snes into develop 2016-02-04 07:11:34 +01:00
Michaël Larouche
6f601e371a Implement final specs of MSU-1 resume. Tested on a SD2SNES rev.F. 2016-01-31 15:20:42 -05:00
Michaël Larouche
c34c4fae66 Merge remote-tracking branch 'upstream/develop' into develop 2016-01-31 12:07:47 -05:00
borti4938
12bf93e444 Merge branch 'develop' of https://github.com/mrehkopf/sd2snes into develop 2015-10-23 10:21:50 +02:00
ikari_01
dedcb9ff5e DAC: volume boost setting for MSU1 2015-10-21 00:12:30 +02:00
Michaël Larouche
5fc6f3462b First draft of the MSU-1 resume prototype on the SD2SNES, not tested because I can't get the firmware to link on either Linux or OS X 2015-09-22 07:30:23 -04:00
borti4938
5bd8a0b2d2 Merge branch 'develop' of https://github.com/mrehkopf/sd2snes into develop 2015-08-31 18:02:59 +02:00
ikari_01
688bd5d6e5 Sample SNES data input to reliably get valid data on writes 2015-08-29 14:52:41 +02:00
ikari_01
22e07425e6 Cx4: Remove all core related multi-cycle constraints; timing closure 2015-08-29 14:52:01 +02:00
ikari_01
3175c55919 Lower clock speed from 88MHz to 86MHz 
(to help achieve timing closure on the dreaded Cx4)
 2015-08-29 14:50:39 +02:00
ikari_01
e47c026813 Give 1MB of writable memory to the menu 2015-08-29 14:48:13 +02:00
borti4938
278a168427 adaptation: project files 2015-08-13 13:12:25 +02:00
borti4938
604a5d98d2 adaptation: header 2015-08-13 13:11:49 +02:00
ikari_01
412127ed5f MSU1: set initial volume to 0 (adhere to latest spec) 2015-04-28 18:05:14 +02:00
ikari_01
1d719e6473 FPGA: change address sampling to obtain valid address on cycle end 
This makes the old MSU address increment work again and hopefully fixes
stability problems that occurred since 0.1.7pre1.
 2015-04-28 17:54:44 +02:00
ikari_01
16c870a55d FPGA/cx4: Project file updates, remove some harmful multi-cycle constraints 2015-02-01 09:42:48 +01:00
ikari_01
b64caf555b FPGA/cx4: experimental SRAM mapping 2015-02-01 09:41:51 +01:00
ikari_01
5303c7b0c6 FPGA: remove ChipScope IP cores from project 2015-02-01 09:41:30 +01:00
ikari_01
8540cf0032 FPGA: adjust in-game hook addresses 2015-02-01 09:39:53 +01:00
ikari_01
84ff37945d FPGA: hide BRAM area from software unless unlocked 
Some games don't like to see the BRAM area (containing the hook routine
and some state information) or just plain overwrite it in their init
routines. It is now hidden from software unless:

* the IRQ/NMI vectors are read (unlock for 48 CPU cycles)
* an unlock sequence is written to BRAM.
 2014-12-09 23:41:33 +01:00
ikari_01
ea136be3e2 FPGA: additional waitstates for uPD7725 core 2014-12-09 23:39:02 +01:00
ikari_01
d5aa5e7184 FPGA/DSPx: fix MMIO write priority 2014-10-17 22:37:43 +02:00
ikari_01
4bdcffdfa6 FPGA: reconstitute more aggressive SNES control signal filtering; unify edge detection and data buffering 2014-10-08 00:00:43 +02:00
ikari_01
c59053c452 Implement temporary hook disable after SNES reset 
As was observed with the help of a number of users, many games trip over
the in-game hooks especially at boot-up. This feature keeps the hooks
disabled for 10 seconds after SNES startup or reset.
 2014-10-07 23:58:42 +02:00
ikari_01
0a85452140 FPGA/cx4: remove init file (debug code) from program ROM block ram 2014-10-04 09:03:21 +02:00
ikari_01
278eedca6b Snoop $4200 register write (sense auto joypad read); double BRAM buffer size 
Rearrange memory map of BRAM hook
 2014-09-30 17:46:42 +02:00
ikari_01
ce4c0dce67 Add missing ISE project files 2014-09-26 17:57:40 +02:00
ikari_01
c1f216f680 FPGA: properly synchronize asynchronous FSM control signals 
hopefully REALLY eliminate FSM lockups this time
 2014-09-25 00:39:26 +02:00
ikari_01
a55a161a2b FPGA: Auto-choose NMI/IRQ vector depending on usage by SNES; 
also do not switch vector patching while vectors are being read
 2014-09-25 00:36:44 +02:00
ikari_01
eb7bf7321c Add missing cheat.v for cx4 and obc1 2014-09-25 00:32:15 +02:00
ikari_01
af77909243 BSX: fix PSRAM mapping, emulate Type 1 memory pack instead of Type 2 
A bug in the BS-X BIOS keeps it from working with HiROM games marked as
"run from PSRAM" used together with Type 2 memory packs. Thus memory
pack Type 1 is now used (different command set).
PSRAM was incorrectly mirrored to banks 00-3f in HiROM mode.
 2014-09-25 00:29:44 +02:00
ikari_01
5350a9f0ab in game hook optimizations/fixes (space, time, realtime vectors) 
Original ROM vectors are now determined at runtime by momentarily
disabling the vector patching and copying them to the jump statements.
To potentially save raster time, joypad is not read manually when auto
joypad read is in place - the results of auto joypad read are used
instead.
Also controller is only read every 8 hook calls to further improve
compatibility.
Addresses are adjusted for space optimizations.
 2014-09-25 00:22:57 +02:00
ikari_01
5e3cdcdb87 FPGA/cx4: add table ROM initialization file 2014-09-18 17:40:05 +02:00
ikari_01
71c401789e FPGA: minor cleanup 2014-09-18 17:35:07 +02:00
ikari_01
74852d7446 FPGA: temporary NMI hook disable; prepare for possible IRQ hook 2014-09-18 17:34:02 +02:00
ikari_01
470b286572 FPGA: new memory sharing for all sub configurations; Cx4 speed switch 2014-09-18 17:32:56 +02:00
ikari_01
b627c23ae7 Embed table ROM in Cx4 core (cx4.bin no longer required); 
Add long missing mcu_cmd.v to cx4 tree
 2014-09-18 17:17:35 +02:00
ikari_01
b9399a6d58 FPGA/cx4: actually interpret feature bit for $213F patching (was always enabled) 2014-08-06 16:19:55 +02:00
ikari_01
2470f8494b FPGA: actually add cheat source code 2014-08-05 09:38:59 +02:00
ikari_01
e675d51235 FPGA/upd77c25: format state constants 2014-08-05 09:37:17 +02:00
ikari_01
4784d5cdc7 FPGA: hopefully eliminate occasional FSM deadlock on bootup 2014-08-05 09:36:55 +02:00
ikari_01
fa84154753 FPGA: cheat engine (ROM cheats / NMI hook) 2014-08-05 09:36:31 +02:00
ikari_01
e4672a7938 FPGA: fix BS-X/Satellaview support for new memory sharing 2014-08-05 09:32:32 +02:00
ikari_01
bdd17c0cd2 FPGA: 64k "SRAM" area for menu memory map 2014-08-05 09:29:28 +02:00
ikari_01
d5b43dfc6a FPGA: new command interface in block RAM, ROM/WRAM independent 2014-06-19 09:24:34 +02:00
ikari_01
ddbbdca2d4 FPGA: simplify memory sharing 
should be less timing critical and more stable on a wide range of consoles
 2014-06-19 09:21:53 +02:00
Maximilian Rehkopf
1dcdf19143 FPGA/diagnostics: correct timespec 2014-05-10 17:17:44 +02:00
Maximilian Rehkopf
c530f5d7c9 FPGA: code formatting + cleanup 2014-05-10 17:17:25 +02:00