mirror of
https://github.com/mrehkopf/sd2snes.git
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95 lines
2.8 KiB
Verilog
95 lines
2.8 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input CLK,
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input [15:0] featurebits,
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input [2:0] MAPPER, // MCU detected mapper
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input [23:0] SNES_ADDR, // requested address from SNES
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input [7:0] SNES_PA, // peripheral address from SNES
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input SNES_ROMSEL, // ROMSEL from SNES
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output [23:0] ROM_ADDR, // Address to request from SRAM0
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output ROM_HIT, // want to access RAM0
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output IS_SAVERAM, // address/CS mapped as SRAM?
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output IS_ROM, // address mapped as ROM?
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output IS_WRITABLE, // address somehow mapped as writable area?
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input [23:0] SAVERAM_MASK,
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input [23:0] ROM_MASK,
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output msu_enable,
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output cx4_enable,
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output cx4_vect_enable,
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output r213f_enable,
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output r2100_hit,
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output snescmd_enable,
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output nmicmd_enable,
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output return_vector_enable,
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output branch1_enable,
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output branch2_enable,
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output branch3_enable
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);
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parameter [2:0]
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FEAT_MSU1 = 3,
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FEAT_213F = 4,
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FEAT_2100 = 6
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;
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wire [23:0] SRAM_SNES_ADDR;
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/* Cx4 mapper:
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- LoROM (extended to 00-7d, 80-ff)
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- MMIO @ 6000-7fff
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- SRAM @ 70-77:0000-7fff
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*/
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assign IS_ROM = ~SNES_ROMSEL;
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assign IS_SAVERAM = |SAVERAM_MASK & (~SNES_ADDR[23] & &SNES_ADDR[22:20] & ~SNES_ADDR[19] & ~SNES_ADDR[15]);
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assign SRAM_SNES_ADDR = IS_SAVERAM
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? (24'hE00000 | ({SNES_ADDR[19:16], SNES_ADDR[14:0]}
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& SAVERAM_MASK))
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: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
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& ROM_MASK);
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assign ROM_ADDR = SRAM_SNES_ADDR;
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assign IS_WRITABLE = IS_SAVERAM;
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assign ROM_HIT = IS_ROM | IS_WRITABLE;
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wire msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
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assign msu_enable = msu_enable_w;
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wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
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assign cx4_enable = cx4_enable_w;
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assign cx4_vect_enable = &SNES_ADDR[15:5];
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assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
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assign r2100_hit = (SNES_PA == 8'h00);
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assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
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assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
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assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
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assign branch1_enable = (SNES_ADDR == 24'h002A1F);
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assign branch2_enable = (SNES_ADDR == 24'h002A59);
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assign branch3_enable = (SNES_ADDR == 24'h002A5E);
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endmodule
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