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sd2snes/verilog/sd2snes_sa1/msu.v
Maximilian Rehkopf 5b0f22d411 Ensure MSU-1 data address increment at end of DMA (#208) 
* Ensure MSU-1 data address increment at end of DMA

* fix MSU1 address increment for rest of the FPGA cores

* update generated files
2023-03-30 11:09:25 +02:00

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