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sd2snes/verilog/sd2snes_sa1/sa1.v
redguyyyy 1a071bbd8a Added CCNT_RESB (wait bit) implementation. Halts SA-1 instruction execute 
after last completed op without redirection to reset vector on resume.
No known use in commercial games.
2023-03-07 22:35:36 +01:00

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