mirror of
https://github.com/mrehkopf/sd2snes.git
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2474621d5f
Both "HiROM" and "LoROM" style mapping are supported by S-DD1. Also remove redundant code and connections for address decoder.
117 lines
3.7 KiB
Verilog
117 lines
3.7 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input [15:0] featurebits, // peripheral enable/disable
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input [23:0] SNES_ADDR, // requested address from SNES
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input [7:0] SNES_PA, // peripheral address from SNES
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input SNES_ROMSEL, // ROMSEL from SNES
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output [23:0] ROM_ADDR, // Address to request from SRAM0
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output ROM_HIT, // enable SRAM0
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output IS_SAVERAM, // address/CS mapped as SRAM?
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output IS_ROM, // address mapped as ROM?
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output IS_WRITABLE, // address somehow mapped as writable area?
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input [23:0] SAVERAM_MASK,
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input [23:0] ROM_MASK,
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output msu_enable,
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output r213f_enable,
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output r2100_hit,
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output snescmd_enable,
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output nmicmd_enable,
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output return_vector_enable,
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output branch1_enable,
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output branch2_enable,
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output branch3_enable
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);
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/* feature bits. see src/fpga_spi.c for mapping */
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parameter [2:0]
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FEAT_MSU1 = 3,
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FEAT_213F = 4
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;
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wire [23:0] SRAM_SNES_ADDR;
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/*
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S-DD1 memory mapper.
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NOTE: Part of the ROM mapping/bankswitching is carried out in SDD1.vhd!
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SaveRAM mapping is still defined here.
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*/
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// active high to select ROM in banks 00-3f,80-bf:8000-ffff and 40-7d,c0-ff:0000-ffff
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// (decoded by SNES)
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assign IS_ROM = ~SNES_ROMSEL;
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/* Save RAM mapping: up to 1Mbit;
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Address ranges: 70-73:0000-7fff,
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00-3f:6000-7fff,
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80-bf:6000-7fff.
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Mirrored like this:
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( x = 0,1,2,3,8,9,a,b )
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70:0000 - x0:6000
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70:1fff - x0:7fff
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70:2000 - x1:6000
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70:3fff - x1:7fff
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...
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70:7fff - x3:7fff
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71:0000 - x4:6000
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71:7fff - x4:7fff
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...
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73:0000 - xc:6000
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...
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73:7fff - xf:7fff
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*/
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wire IS_SAVERAM_BIGBANKS = ((SNES_ADDR[23:18] == 6'b011100) && (SNES_ADDR[15] == 1'b0));
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wire IS_SAVERAM_SMALLBANKS = ((SNES_ADDR[22] == 1'b0) && (SNES_ADDR[15:13] == 3'b011));
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wire [1:0] SAVERAM_BANK_BIG = SNES_ADDR[17:16];
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wire [3:0] SAVERAM_BANK_SMALL = SNES_ADDR[19:16];
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wire [14:0] SAVERAM_OFFSET_BIG = SNES_ADDR[14:0];
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wire [12:0] SAVERAM_OFFSET_SMALL = SNES_ADDR[12:0];
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assign IS_SAVERAM = IS_SAVERAM_BIGBANKS | IS_SAVERAM_SMALLBANKS;
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// '1' to signal access to cartrigde writable range (Backup RAM or BS-X RAM)
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assign IS_WRITABLE = IS_SAVERAM;
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assign SRAM_SNES_ADDR = IS_SAVERAM_BIGBANKS ? 24'hE00000 + ({SAVERAM_BANK_BIG, SAVERAM_OFFSET_BIG} & SAVERAM_MASK)
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: IS_SAVERAM_SMALLBANKS ? 24'hE00000 + ({SAVERAM_BANK_SMALL, SAVERAM_OFFSET_SMALL} & SAVERAM_MASK)
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: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK);
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assign ROM_ADDR = SRAM_SNES_ADDR;
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// '1' when accesing PSRAM for ROM, Backup RAM, BS-X RAM
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assign ROM_HIT = IS_ROM | IS_WRITABLE;
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// '1' when accessing to MSU register map $2000:$2007
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assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
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assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
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assign r2100_hit = (SNES_PA == 8'h00);
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assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
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assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
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assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
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assign branch1_enable = (SNES_ADDR == 24'h002A1F);
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assign branch2_enable = (SNES_ADDR == 24'h002A59);
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assign branch3_enable = (SNES_ADDR == 24'h002A5E);
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endmodule
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