2022-09-02 13:21:39 +02:00
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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2022-09-23 23:10:36 +02:00
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#include <gpu/descriptor_allocator.h>
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2022-11-18 22:03:02 +01:00
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#include <gpu/interconnect/common/samplers.h>
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2022-11-18 22:13:49 +01:00
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#include <gpu/interconnect/common/textures.h>
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2022-09-02 13:21:39 +02:00
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#include "common.h"
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#include "active_state.h"
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#include "constant_buffers.h"
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namespace skyline::gpu::interconnect::maxwell3d {
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/**
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* @brief The core Maxwell 3D interconnect object, directly accessed by the engine code to perform rendering operations
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*/
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class Maxwell3D {
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public:
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struct ClearEngineRegisters {
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const engine::Scissor &scissor0;
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const engine::ViewportClip &viewportClip0;
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const engine::ClearRect &clearRect;
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const std::array<u32, 4> &colorClearValue;
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const float &depthClearValue;
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const u32 &stencilClearValue;
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const engine::SurfaceClip &surfaceClip;
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const engine::ClearSurfaceControl &clearSurfaceControl;
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};
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/**
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* @brief The full set of register state used by the GPU interconnect
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*/
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struct EngineRegisterBundle {
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ActiveState::EngineRegisters activeStateRegisters;
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ClearEngineRegisters clearRegisters;
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ConstantBufferSelectorState::EngineRegisters constantBufferSelectorRegisters;
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SamplerPoolState::EngineRegisters samplerPoolRegisters;
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const engine::SamplerBinding &samplerBinding;
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TexturePoolState::EngineRegisters texturePoolRegisters;
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};
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private:
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InterconnectContext ctx;
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ActiveState activeState;
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ClearEngineRegisters clearEngineRegisters;
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ConstantBuffers constantBuffers;
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Samplers samplers;
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const engine::SamplerBinding &samplerBinding;
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Textures textures;
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2022-09-29 21:50:47 +02:00
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std::shared_ptr<memory::Buffer> quadConversionBuffer{};
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bool quadConversionBufferAttached{};
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2023-02-04 23:32:36 +01:00
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BufferView indirectBufferView;
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2022-10-09 14:58:50 +02:00
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static constexpr size_t DescriptorBatchSize{0x100};
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std::shared_ptr<boost::container::static_vector<DescriptorAllocator::ActiveDescriptorSet, DescriptorBatchSize>> attachedDescriptorSets;
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DescriptorAllocator::ActiveDescriptorSet *activeDescriptorSet{};
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2022-10-30 17:15:00 +01:00
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std::vector<TextureView *> activeDescriptorSetSampledImages{};
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2022-09-29 21:50:47 +02:00
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size_t UpdateQuadConversionBuffer(u32 count, u32 firstVertex);
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2023-03-04 22:11:35 +01:00
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/**
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* @brief A scissor derived from the current clear register state
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*/
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vk::Rect2D GetClearScissor();
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2023-03-04 22:11:35 +01:00
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/**
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* @brief A scissor derived from the current draw register state and bound RTs
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*/
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vk::Rect2D GetDrawScissor();
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/**
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* @brief Performs operations common across indirect and regular draws
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*/
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void PrepareDraw(StateUpdateBuilder &builder,
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engine::DrawTopology topology, bool indexed, bool estimateIndexBufferSize, u32 firstIndex, u32 count,
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vk::PipelineStageFlags &srcStageMask, vk::PipelineStageFlags &dstStageMask);
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2022-09-02 13:21:39 +02:00
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public:
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DirectPipelineState &directState;
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Maxwell3D(GPU &gpu,
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soc::gm20b::ChannelContext &channelCtx,
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nce::NCE &nce,
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kernel::MemoryManager &memoryManager,
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DirtyManager &manager,
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const EngineRegisterBundle ®isterBundle);
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/**
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* @brief Loads the given data into the constant buffer pointed by the constant buffer selector starting at the given offset
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*/
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void LoadConstantBuffer(span<u32> data, u32 offset);
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/**
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* @brief Binds the constant buffer selector to the given pipeline stage
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*/
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2022-09-10 21:29:47 +02:00
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void BindConstantBuffer(engine::ShaderStage stage, u32 index, bool enable);
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2022-09-18 17:14:24 +02:00
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/**
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* @note See ConstantBuffers::DisableQuickBind
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*/
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void DisableQuickConstantBufferBind();
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void Clear(engine::ClearSurface &clearSurface);
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2022-10-09 15:07:00 +02:00
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void Draw(engine::DrawTopology topology, bool transformFeedbackEnable, bool indexed, u32 count, u32 first, u32 instanceCount, u32 vertexOffset, u32 firstInstance);
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2023-02-04 23:32:36 +01:00
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void DrawIndirect(engine::DrawTopology topology, bool transformFeedbackEnable, bool indexed, span<u8> indirectBuffer, u32 count, u32 stride);
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};
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}
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