Commit Graph

79 Commits

Author SHA1 Message Date
PixelyIon
2a8bcc60c7 Make Render Targets Abstract for Color/Depth RTs
This prefixes all RT functions that deal with color RTs with `Color` and abstracts out common functions that will be used for both color and depth RTs. All common Maxwell3D structures are also moved out of the `ColorRenderTarget` (`RenderTarget` previously) structure.
2022-04-14 14:14:52 +05:30
PixelyIon
4dcf12c4c0 Implement Maxwell3D Draws
Uses all Maxwell3D state converted into Vulkan state to do an equivalent draw on the host GPU, it sets up RT/Vertex Buffer/Vertex Attribute/Shader state and creates a stubbed out `VkPipelineLayout` for the draw. Any descriptor state isn't currently handled and is yet to be implemented, currently there's no Vulkan pipeline cache supplied which will be implemented subsequently.
2022-04-14 14:14:52 +05:30
PixelyIon
38119e21d4 Implement Vulkan-Supported Maxwell3D Primitive Topologies
Any primitive topologies that are directly supported by Vulkan were implemented but the rest were not and will be implemented with conversions as they are used by applications, they are:
* LineLoop
* QuadList
* QuadStrip
* Polygon
2022-04-14 14:14:52 +05:30
PixelyIon
138f884159 Implement Maxwell3D Vertex Attributes
Translates all Maxwell3D vertex attributes to Vulkan with the exception of `isConstant` which causes the vertex attribute to return a constant value `(0,0,0,X)` which was trivial in OpenGL with `glDisableVertexAttribArray` and `glVertexAttrib4(..., 0, 0, 0, 1)` but we don't have access to this in Vulkan and might need to depend on undefined behavior or manually emulate it in a shader. This'll be revisited in the future after checking host GPU behavior.
2022-04-14 14:14:52 +05:30
PixelyIon
c2a6da6431 Implement Maxwell3D Vertex Buffer Limit
Sets the end of VBOs based on the `vertexArrayLimits` register array which provides an IOVA to the end of the VBO.
2022-04-14 14:14:52 +05:30
PixelyIon
612f324e78 Implement Maxwell3D Vertex Buffer Instance Rate
Implements the `isVertexInputRatePerInstance` register array which controls if the vertex input rate is either per-vertex or per-instance. This works in conjunction with the vertex attribute divisor for per-instance attribute repetition of attributes.
2022-04-14 14:14:52 +05:30
PixelyIon
476c070c7a Fix Minor Maxwell3D Register Ordering Issues
We order all registers in ascending order, a few registers namely `colorLogicOp`, `colorWriteMask`, `clearBuffers` and `depthBiasClamp` were erroneously not following this order which has now been fixed.
2022-04-14 14:14:52 +05:30
PixelyIon
ff5515d4d1 Implement Maxwell3D Vertex Buffer Bindings
This implements everything in Maxwell3D vertex buffer bindings including vertex attribute divisors which require the extension `VK_EXT_vertex_attribute_divisor` to emulate them correctly, this has been implemented in the form of of a quirk. It is dynamically enabled/disabled based on if the host GPU supports it and a warning is provided when it is used by the guest but the host GPU doesn't support it.
2022-04-14 14:14:52 +05:30
PixelyIon
48d0b41f16 Implement Maxwell3D Common/Independent Color Write Mask
Maxwell3D supports both independent and common color write masks like color blending but for common color write masks rather than having register state specifically for it, the state from RT 0 is extended to all RTs. It should be noted that color write masks are included in blending state for Vulkan while being entirely independent from each other for Maxwell, it forces us to use the `independentBlend` feature even when we are doing common blending unless the color write mask is common as well but to simplify all this logic the feature was made required as it supported by effectively all targeted devices.
2022-04-14 14:14:52 +05:30
PixelyIon
92809f8a78 Implement Maxwell3D Independent/Common Color Blending
Maxwell3D supports independent blending which has different blending per-RT and common blending which has the same blending for all RTs. There is a register determining which mode to utilize and we simply have two arrays of `VkPipelineColorBlendAttachmentState` for the RTs that we toggle between to make the transition between them extremely cheap.
2022-04-14 14:14:52 +05:30
PixelyIon
6099b1ead5 Fix Maxwell3D Register lineWidthAliased Offset
The offset was incorrectly set to `0x4D` rather than `0x4ED` which is what it should be. This would've led to bugs in line width determination and likely broken any aliased line rendering entirely.
2022-04-14 14:14:52 +05:30
PixelyIon
ec378814aa Stub Maxwell3D Alpha Testing
We stub alpha testing as it doesn't exist in Vulkan and few titles use it, it can be emulated in the future using a shader patch with manually discarding fragments failing the alpha test function but this'll be added in later as it isn't high priority at the moment and has associated overhead with it so other options might be explored at the time.
2022-04-14 14:14:52 +05:30
PixelyIon
01eb16e59a Implement Maxwell3D Color Logic Operations
Implements a basic part of Vulkan blending state which are color logic operations applied on the framebuffer after running the fragment shader. It is an optional feature in Vulkan and not supported on any mobile GPU vendor aside from ImgTec/NVIDIA by default.
2022-04-14 14:14:52 +05:30
PixelyIon
586bee2c59 Remove Maxwell3D Zero Initialization Calls
A lot of calls in Maxwell3D register initialization ended up setting the register to 0 which should be implicit behavior and most calls would be eliminated by the redundancy check which had to be manually disabled. It was determined to be better to move this responsibility to the called function to initialize to state equivalent to the corresponding register being 0. All initialization calls with the argument as 0 have been removed now due to this, it was the vast majority of calls.
2022-04-14 14:14:52 +05:30
PixelyIon
49cc0964e2 Initialize Maxwell3D Registers Correctly
Maxwell3D Registers weren't initialized to the correct values prior, this commit fixes that by doing `HandleMethod` calls with all the register values being initialized. This is in contrast to the registers being set without calling the methods in `GraphicsContext` or otherwise resulting in bugs.
2022-04-14 14:14:52 +05:30
PixelyIon
5ed26fef23 Implement Maxwell3D Rasterizer State
Maxwell3D registers relevant to the Vulkan Rasterizer state have been implemented aside from certain features such as per-face polygon modes that cannot be implemented due to Vulkan limitations. A quirk was utilized to dynamically support the provoking vertex being the last vertex as opposed to the first as well.
2022-04-14 14:14:52 +05:30
PixelyIon
26966287c7 Implement Maxwell3D Shader Program Registers
This commit added basic shader program registers, they simply track the address a shader is pointed to at the moment. No parsing of the shader program is done within them.
2022-04-14 14:14:52 +05:30
PixelyIon
fbfad21f03 Migrate Maxwell3D::Registers to OffsetMember
Maxwell3D registers were primarily written with absolute offsets and ended up being fairly messy due to attempting to emulate this using struct relative positioning resulting in a lot of pointless padding members. This has now been improved by utilizing `OffsetMember` to directly use offsets resulting in much neater code.
2021-11-10 21:31:45 +05:30
Billy Laws
eb25f60033 Implement multichannel support for GPU
Allows the execution of multiple channels at the same time, with locking
being performed on the host GPU scheduler layer, address spaces can be
bound to one or more channels.
2021-10-16 12:13:30 +01:00
PixelyIon
f8acc1e131 Improve Shared Fonts + Fix AM PopLaunchParameter & Choreographer Bug
* Move Shared Font TTFs to AAsset storage + Support external shared font loading from `/data/data/skyline.emu/data/fonts`
* Fix bug in `IApplicationFunctions::PopLaunchParameter` caused by ignoring `LaunchParameterKind`
* Fix bug with Choreographer causing it to be awoken and exit prior to the destruction of `PresentationEngine`
* Fix bug with `IDirectory::Read` where it used `inputBuf` for the output buffer rather than `outputBuf`
* Improve `GetFunctionStackTrace` logs when `dli_sname` or `dli_fname` are missing
* Support more RT Formats
2021-10-16 12:13:30 +01:00
PixelyIon
239d2625e2 Introduce CommandExecutor + Implement ClearBuffers + More RT Formats
This commit introduces the `CommandExecutor` which is responsible for creating and orchestrating a Vulkan command graph comprising of `CommandNode`s that construct all the objects required for rendering. As a result of the infrastructure provided by `CommandExecutor`, `ClearBuffers` could be implemented and be appropriately utilized.

A bug regarding scissors was also determined and fixed in the PR, the extent of them were previously inaccurate and this has now been fixed.

Note: We don't synchronize any textures from the guest for now as this would override the contents on the host, this'll be fixed with the appropriate write tracking but it also results in a black screen for anything that writes to FB
2021-10-05 01:13:22 +05:30
PixelyIon
54908afc44 Texture GMMU Address Resolution + Refactor Maxwell3D::CallMethod
Fixes bugs with the Texture Manager lookup, fixes `RenderTarget` address extraction (`low`/`high` were flipped prior), refactors `Maxwell3D::CallMethod` to utilize a case for the register being modified + preventing redundant method calls when no new value is being written to the register, and fixes the behavior of shadow RAM which was broken previously and would lead to incorrect arguments being utilized for methods.
2021-10-05 01:13:22 +05:30
PixelyIon
270f2db1d2 Initial Texture Manager Implementation + Maxwell3D Render Target
Implement the groundwork for the texture manager to be able to report basic overlaps and be extended to support more in the future. The Maxwell3D registers `RenderTargetControl`, `RenderTarget` and a stub for `ClearBuffers` were implemented. 

A lot of changes were also made to `GuestTexture`/`Texture` for supporting mipmapping and multiple array layers alongside significant architectural changes to `GuestTexture` effectively disconnecting it from `Texture` with it no longer being a parent rather an object that can be used to create a `Texture` object.

Note: Support for fragmented CPU mappings hasn't been added for texture synchronization yet
2021-10-05 01:13:22 +05:30
PixelyIon
190fde110f Introduce GraphicContext and Implement Viewport Transform + Scissors 2021-10-05 01:13:22 +05:30
Billy Laws
a4a6511177 Address feedback 2021-09-30 02:11:19 +05:30
Billy Laws
39faa739b9 Optimise GPFIFO command processing for higher throughput
Using a u32 for the loop index prevents masking on all increments,
giving a moderate performance increase.

Passing methods as u32 parameters and stopping subChannel being passed
gives quite a significant increase when combined with the inlining
allowed by subchannel based engine selection.
2021-09-30 02:11:19 +05:30
PixelyIon
d8025e7178 Rework GraphicBufferProducer
This commit makes GraphicBufferProducer significantly more accurate by matching the behavior of AOSP alongside mirroring the tweaks made by Nintendo. 

It eliminates a lot of the magic structures and enumerations used prior and replaces them with the correct values from AOSP or HOS. 

There was a lot of functional inaccuracy as well which was fixed, we emulate the exact subset of HOS behavior that we need to. A lot of the intermediate layers such as GraphicBufferConsumer or Gralloc/Sync are not emulated as they're pointless abstractions here.
2021-07-12 21:27:49 +05:30
PixelyIon
8056b80073 Address CR Comments (#151) + Fix SvcWaitSynchronization Trace
An RAII scoped trace was used for SvcWaitSynchronization but it was placed within a condition scope which led to an incorrect lifetime for the traces. Minor changes regarding the CR not affecting functionality were made aside from that.
2021-03-25 22:57:26 +05:30
PixelyIon
3f7373209a Move Guest GPU into SoC Directory
We decided to restructure Skyline to draw a layer of separation between guest and host GPU. We're reserving the `gpu` namespace and directory for purely host GPU and creating a new `soc` directory and namespace for emulation of parts of the X1 SoC which is currently limited to guest GPU but will be expanded to contain components like the audio DSP down the line.
2021-03-25 22:57:26 +05:30