Commit Graph

504 Commits

Author SHA1 Message Date
PixelyIon
ff5515d4d1 Implement Maxwell3D Vertex Buffer Bindings
This implements everything in Maxwell3D vertex buffer bindings including vertex attribute divisors which require the extension `VK_EXT_vertex_attribute_divisor` to emulate them correctly, this has been implemented in the form of of a quirk. It is dynamically enabled/disabled based on if the host GPU supports it and a warning is provided when it is used by the guest but the host GPU doesn't support it.
2022-04-14 14:14:52 +05:30
PixelyIon
d163e4ffa6 Introduce IOVA union for flipped words of IOVAs in GraphicsContext
The Maxwell3D `Address` class follows the big-endian register ordering for addresses while on the host we consume them in little-endian, the `IOVA` class is the host equivalent to the `Address` class with implicitly flipped 32-bit register ordering. It shares implicit decomposition semantics from `Address` due to similar requirements with a minor difference of being returned by reference rather than value as we want to have value setting semantics with implicit decomposition while we don't for `Address`.
2022-04-14 14:14:52 +05:30
PixelyIon
73646c4da8 Implicitly decompose Address into u64
The semantics of implicitly decomposing the `Address` class into a `u64` were determined to be appropriate for the class. As it is an integer type this effectively retains all semantics from using an integer directly for the most part.
2022-04-14 14:14:52 +05:30
PixelyIon
48d0b41f16 Implement Maxwell3D Common/Independent Color Write Mask
Maxwell3D supports both independent and common color write masks like color blending but for common color write masks rather than having register state specifically for it, the state from RT 0 is extended to all RTs. It should be noted that color write masks are included in blending state for Vulkan while being entirely independent from each other for Maxwell, it forces us to use the `independentBlend` feature even when we are doing common blending unless the color write mask is common as well but to simplify all this logic the feature was made required as it supported by effectively all targeted devices.
2022-04-14 14:14:52 +05:30
PixelyIon
92809f8a78 Implement Maxwell3D Independent/Common Color Blending
Maxwell3D supports independent blending which has different blending per-RT and common blending which has the same blending for all RTs. There is a register determining which mode to utilize and we simply have two arrays of `VkPipelineColorBlendAttachmentState` for the RTs that we toggle between to make the transition between them extremely cheap.
2022-04-14 14:14:52 +05:30
PixelyIon
2ceb6465e8 Make independentBlend a required VkDevice feature
Independent blending is supported by effectively every Vulkan 1.1 Android GPU, it gives us the ability to architecture Maxwell3D blending emulation better as we can avoid additional checks for independent blending state and having a fallback path for when the host doesn't support the feature.
2022-04-14 14:14:52 +05:30
PixelyIon
cd737fbdd8 Add Required VkDevice Features
A prior commit added the ability to utilize features with quirks but this implements the ability to require a feature be present on the host or an exception will be thrown. It allows us to make useful assumptions that result in a better architecture in certain cases.
2022-04-14 14:14:52 +05:30
PixelyIon
081d3277c1 Enable Quirk + Required VkDevice Extensions
Implements the infrastructure required to enable optional extensions set in `QuirkManager` alongside the required extensions in the `GPU` class. All extensions should be correctly resolved now and according to what the device supports.
2022-04-14 14:14:52 +05:30
PixelyIon
6099b1ead5 Fix Maxwell3D Register lineWidthAliased Offset
The offset was incorrectly set to `0x4D` rather than `0x4ED` which is what it should be. This would've led to bugs in line width determination and likely broken any aliased line rendering entirely.
2022-04-14 14:14:52 +05:30
PixelyIon
51659e1329 Enable VkDevice Features Selectively
We selectively enable GPU features that we require as enabling all of them might result in extra driver overhead in certain circumstances. Setting them is handled by `QuirkManager` with the new `FEAT_SET` function that ties a quirk with a feature.
2022-04-14 14:14:52 +05:30
PixelyIon
ec378814aa Stub Maxwell3D Alpha Testing
We stub alpha testing as it doesn't exist in Vulkan and few titles use it, it can be emulated in the future using a shader patch with manually discarding fragments failing the alpha test function but this'll be added in later as it isn't high priority at the moment and has associated overhead with it so other options might be explored at the time.
2022-04-14 14:14:52 +05:30
PixelyIon
83ec99fa48 Print GPU Quirks At Startup
It is essential to know what quirks a certain GPU may have to debug an issue, these are now printed at startup into the log alongside all other GPU information. A new `QuirkManager::Summary` function was implemented to provide this functionality.
2022-04-14 14:14:52 +05:30
PixelyIon
01eb16e59a Implement Maxwell3D Color Logic Operations
Implements a basic part of Vulkan blending state which are color logic operations applied on the framebuffer after running the fragment shader. It is an optional feature in Vulkan and not supported on any mobile GPU vendor aside from ImgTec/NVIDIA by default.
2022-04-14 14:14:52 +05:30
PixelyIon
662935c35d Attempt Flushing Logger During Fatal Signals
Any signals that lead to exception handling being triggered now attempt to flush all logs given that the log mutex is unoccupied, this is to mostly help logs be more complete when exiting isn't graceful.
2022-04-14 14:14:52 +05:30
PixelyIon
586bee2c59 Remove Maxwell3D Zero Initialization Calls
A lot of calls in Maxwell3D register initialization ended up setting the register to 0 which should be implicit behavior and most calls would be eliminated by the redundancy check which had to be manually disabled. It was determined to be better to move this responsibility to the called function to initialize to state equivalent to the corresponding register being 0. All initialization calls with the argument as 0 have been removed now due to this, it was the vast majority of calls.
2022-04-14 14:14:52 +05:30
PixelyIon
49cc0964e2 Initialize Maxwell3D Registers Correctly
Maxwell3D Registers weren't initialized to the correct values prior, this commit fixes that by doing `HandleMethod` calls with all the register values being initialized. This is in contrast to the registers being set without calling the methods in `GraphicsContext` or otherwise resulting in bugs.
2022-04-14 14:14:52 +05:30
PixelyIon
ea87b8878c Implement B8G8R8A8{Unorm/Srgb} RT Format
Needed by Maxwell3D Register Initialization
2022-04-14 14:14:52 +05:30
PixelyIon
69e7d8b574 Remove Vulkan to Skyline Format Conversion Function
The function `GetFormat` was seemingly no longer required due to us never converting from a Vulkan format to a Skyline format, most conversions only went from Skyline to Vulkan and were generally lossy due to certain formats being missing in Vulkan and approximated using channel swizzles. As a result of this, it was pointless to maintain and has now been removed.
2022-04-14 14:14:52 +05:30
PixelyIon
5ed26fef23 Implement Maxwell3D Rasterizer State
Maxwell3D registers relevant to the Vulkan Rasterizer state have been implemented aside from certain features such as per-face polygon modes that cannot be implemented due to Vulkan limitations. A quirk was utilized to dynamically support the provoking vertex being the last vertex as opposed to the first as well.
2022-04-14 14:14:52 +05:30
PixelyIon
8ef225a37d Introduce QuirkManager for runtime GPU quirk tracking
We require a way to track certain host GPU features that are optional such as Vulkan extensions, this is what the `QuirkManager` class does as it checks for all quirks and holds them allowing other components to branch based off these quirks.
2022-04-14 14:14:52 +05:30
PixelyIon
8803616673 Reorder GraphicsContext Members
All members are now placed at the start of sections they are relevant to rather than  at the start of the class.
2022-04-14 14:14:52 +05:30
PixelyIon
107d337d77 Fix MacroInterpreter::MethodAddress Bitfield Padding
Due to compiler alignment issues, the bitfield member `increment` of `MacroInterpreter::MethodAddress` was mistakenly padded and moved to the next byte. This has now been fixed by making its type `u16` like the member prior to it to prevent natural alignment from kicking in.
2022-04-14 14:14:52 +05:30
PixelyIon
26966287c7 Implement Maxwell3D Shader Program Registers
This commit added basic shader program registers, they simply track the address a shader is pointed to at the moment. No parsing of the shader program is done within them.
2022-04-14 14:14:52 +05:30
PixelyIon
93ea919c8f Fix warnings from NVRESULT due to unused lambda capture
A previously used `this` capture is no longer used since the introduction of the static logger.
2022-04-14 14:14:52 +05:30
lynxnb
092dcb18c8 Stub ectx:w and ectx:aw Glue services 2022-02-06 21:57:38 +05:30
lynxnb
6913a90361 Use the new log file name & ext for every logger context 2021-11-11 16:32:19 +01:00
lynxnb
5cd1f01690 Refactor all logger calls 2021-11-11 16:13:24 +01:00
lynxnb
769e6c933d Make Logger class static and introduce LoggerContext
A thread local LoggerContext is now used to hold the output file stream instead of the `Logger` class. Before doing any logging operations, a LoggerContext must be initialized.
This commit will not build successfully on purpose.
2021-11-11 16:13:24 +01:00
Billy Laws
d88b08d986 Address PR feedback 2021-11-10 21:35:36 +05:30
Billy Laws
1b453c04ca Remove completed nvmap TODO
Pins have been implemented so the to-do is no longer needed.
2021-11-10 21:35:36 +05:30
Billy Laws
d2d181725f Remove unused virtEnd variable in FlatMemoryManager::{Read, Write} 2021-11-10 21:35:36 +05:30
Billy Laws
60fbfad4bc Add virtual dtors to time service code 2021-11-10 21:35:36 +05:30
Billy Laws
ef10d3d394 Use semantic wrapping where appropriate for class initialiser lists 2021-11-10 21:35:36 +05:30
Billy Laws
6b33268d85 Remove unused gm20b EngineID enum 2021-11-10 21:35:36 +05:30
Billy Laws
73896c2e6b Fixup nvdrv channel types to follow naming conventions 2021-11-10 21:35:36 +05:30
Billy Laws
ad900aba7a s/Host1X/Host1x/ as per Nvidia naming 2021-11-10 21:35:36 +05:30
Billy Laws
dbfb1cfe20 Fully implement the nvdrv Host1xChannel::Submit operation
This pushes a set of command buffers into the Host1x command FIFO allocated for the channel, returning fence thresholds that can be waited on for completion,
2021-11-10 21:35:36 +05:30
Billy Laws
baefb0fe93 Implement the Host1x command FIFO together with barebones Host1x classes
The Host1x block of the TX1 supports 14 separate channels to which commands can be issued, these all run asynchronously so are emulated the same way as GPU channels with one FIFO emulation thread each. The command FIFO itself is very similar to the GPFIFO found in the GPU however there are some differences, mainly the introduction of classes (similar to engines) and the Mask opcode (which allows writing to a specific set of offsets much more efficiently).

There is an internal Host1x class which functions similar to the GPFIFO class in the GPU, handling general operations such as syncpoint waits, this is accessed via the simple method interface. Other channels such as NVDEC and VIC are behind the 'Tegra Host Interface' (THI) in HW, this abstracts out the classes internal details and provides a uniform method interface ontop of the Host1x method one. We emulate the THI as a templated wrapper for the underlying class.

Syncpoint increments in Host1x are different to GPU, the THI allows submitting increment requests that will be queued up and only be applied after a specific condition in the associated engine is met; however the option to for immediate increments is also available.
2021-11-10 21:35:36 +05:30
Billy Laws
2494cafee8 Cleanup GPFIFO comments and make Run() private 2021-11-10 21:35:36 +05:30
Billy Laws
2577658fc7 Avoid GetPointer on nvmap handles where they would be accessed via SMMU
GetPointer sets the sharedMemMapped flag, which should only be set if
other userspace processes have the handle mapped.
2021-11-10 21:35:36 +05:30
Billy Laws
fd0420443c Add template utils for constructing all elements in an std::array
This avoids the excessive repetition needed for the case where array
members have no default constructor.

eg:
```c++
std::array<Type, 10> channels{util::MakeFilledArray<Type, 10>(typeConstructorArg, <...>)};
```
2021-11-10 21:35:36 +05:30
Billy Laws
34bf413661 Fix bitmask check for event IDs > 32 in Ctrl::SyncpointFreeEventBatch
Doing 1 << 32 would result in an integer overflow rather than the desired behaviour of checking a bit, make 1 64 bit to present that.
2021-11-10 21:34:30 +05:30
Billy Laws
debab7c9c7 Implement nvmap handle pinning/unpinning
nvmap allows mapping handles into the SMMU address space through 'pins'. These are refcounted mappings that are lazily freed when required due to AS space running out. Nvidia implements this by using several MRU lists of handles in order to choose which ones to free and which ones to keep, however as we are unlikely to even run into the case of not having enough address space a naive queue approach works fine. This pin infrastructure is used by nvdrv's host1x channel implementation in order to handle mapping of both command and data buffers for submit.
2021-11-10 21:34:30 +05:30
Billy Laws
a0c57256cc Hookup FlatMemoryManager for SMMU into SoC
The SMMU is used to control the mappings of peripherals such as the VIC
and NVDEC.
2021-11-10 21:34:30 +05:30
Billy Laws
97dc053ffd Move FlatAllocator allocation error handling to the caller
This is a prerequisite for nvmap SMMU memory management, which only frees the memory handles refer to if an allocation fails.
2021-11-10 21:34:30 +05:30
Billy Laws
04e5237ec1 Stub host1x channel devices and IOCTLs
host1x channels are generally similar to GPU channels however there is only one channel for each specific class (like a GPU engine) and an address space is shared between them all.

This PR implements the simple IOCTLs with the larger ones that will depend on changes outside of nvdrv being left for future commits. This is enough to partly run oss-nvjpeg.
2021-11-10 21:34:30 +05:30
Billy Laws
5087d3dc2a Reserve host1x channel syncpoints 2021-11-10 21:34:30 +05:30
Billy Laws
b0a5dab0f7 Support passing additional constructor arguments to nvdrv devices
Needed for host1x channels which use the same class for multiple types.
2021-11-10 21:34:30 +05:30
Billy Laws
eb6f052873 Fixup GpuChannel::SetNvmapFd to take an FD rather than an nvmap handle 2021-11-10 21:34:30 +05:30
Billy Laws
386a3447a8 Introduce variable sized span support to nvdrv deserialisation
The element containing the size first needs to be saved to a save slot with Save<T, slotId>, it can then be read back later as the size of a span with SlotSizeSpan<T, slotId>. This is needed to support the Host1XChannel Submit IOCTL.
2021-11-10 21:34:30 +05:30