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// SPDX-License-Identifier: MPL-2.0
// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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// Copyright © 2022 Ryujinx Team and Contributors (https://github.com/Ryujinx/)
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// Copyright © 2018-2020 fincs (https://github.com/devkitPro/deko3d)
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# pragma once
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# include <gpu/interconnect/maxwell_3d/maxwell_3d.h>
# include <soc/host1x/syncpoint.h>
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# include "engine.h"
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# include "inline2memory.h"
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# include "maxwell/types.h"
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namespace skyline : : soc : : gm20b {
struct ChannelContext ;
}
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namespace skyline : : soc : : gm20b : : engine : : maxwell3d {
/**
* @ brief The Maxwell 3 D engine handles processing 3 D graphics
*/
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class Maxwell3D : public MacroEngineBase {
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private :
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host1x : : SyncpointSet & syncpoints ;
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Inline2MemoryBackend i2m ;
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gpu : : interconnect : : DirtyManager dirtyManager ;
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gpu : : interconnect : : maxwell3d : : Maxwell3D interconnect ;
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union BatchEnableState {
u8 raw { } ;
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struct {
bool constantBufferActive : 1 ;
bool drawActive : 1 ;
} ;
} batchEnableState { } ;
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struct BatchLoadConstantBufferState {
std : : vector < u32 > buffer ;
u32 startOffset { } ;
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void Reset ( ) {
buffer . clear ( ) ;
}
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} batchLoadConstantBuffer ; //!< Holds state for updating constant buffer data in a batch rather than word by word
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/**
* @ brief In the Maxwell 3 D engine , instanced draws are implemented by repeating the exact same draw in sequence with special flag set in vertexBeginGl . This flag allows either incrementing the instance counter or resetting it , since we need to supply an instance count to the host API we defer all draws until state changes occur . If there are no state changes between draws we can skip them and count the occurences to get the number of instances to draw .
*/
struct DeferredDrawState {
bool indexed ; //!< If the deferred draw is indexed
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type : : DrawTopology drawTopology ; //!< Topology of draw at draw time
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u32 instanceCount { 1 } ; //!< Number of instances in the final draw
u32 drawCount ; //!< indexed ? drawIndexCount : drawVertexCount
u32 drawFirst ; //!< indexed ? drawIndexFirst : drawVertexFirst
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u32 drawBaseVertex ; //!< Only applicable to indexed draws
u32 drawBaseInstance ;
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/**
* @ brief Sets up the state necessary to defer a new draw
*/
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void Set ( u32 pDrawCount , u32 pDrawFirst , u32 pDrawBaseVertex , u32 pDrawBaseInstance , type : : DrawTopology pDrawTopology , bool pIndexed ) {
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indexed = pIndexed ;
drawTopology = pDrawTopology ;
drawCount = pDrawCount ;
drawFirst = pDrawFirst ;
drawBaseVertex = pDrawBaseVertex ;
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drawBaseInstance = pDrawBaseInstance ;
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}
} deferredDraw { } ;
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type : : DrawTopology ApplyTopologyOverride ( type : : DrawTopology beginMethodTopology ) ;
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void FlushDeferredDraw ( ) ;
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/**
* @ brief Calls the appropriate function corresponding to a certain method with the supplied argument
*/
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void HandleMethod ( u32 method , u32 argument ) ;
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public :
/**
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* @ url https : //github.com/devkitPro/deko3d/blob/master/source/maxwell/engine_3d.def
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*/
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# pragma pack(push, 1)
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union Registers {
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std : : array < u32 , EngineMethodsEnd > raw ;
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template < size_t Offset , typename Type >
using Register = util : : OffsetMember < Offset , Type , u32 > ;
Register < 0x40 , u32 > noOperation ;
Register < 0x44 , u32 > waitForIdle ;
struct MME {
u32 instructionRamPointer ; // 0x45
u32 instructionRamLoad ; // 0x46
u32 startAddressRamPointer ; // 0x47
u32 startAddressRamLoad ; // 0x48
type : : MmeShadowRamControl shadowRamControl ; // 0x49
} ;
Register < 0x45 , MME > mme ;
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Register < 0x60 , Inline2MemoryBackend : : RegisterState > i2m ;
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Register < 0x84 , u32 > apiMandatedEarlyZEnable ;
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Register < 0xB2 , type : : SyncpointAction > syncpointAction ;
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struct DrawZeroIndex {
u32 count ;
} ;
Register < 0xC1 , DrawZeroIndex > drawZeroIndex ;
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Register < 0xC8 , type : : TessellationParameters > tessellationParameters ;
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Register < 0xDF , u32 > rasterEnable ;
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Register < 0xE0 , std : : array < type : : StreamOutBuffer , type : : StreamOutBufferCount > > streamOutBuffers ;
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Register < 0x1C0 , std : : array < type : : StreamOutControl , type : : StreamOutBufferCount > > streamOutControls ;
Register < 0x1D1 , u32 > streamOutputEnable ;
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Register < 0x200 , std : : array < type : : ColorTarget , type : : ColorTargetCount > > colorTargets ;
Register < 0x280 , std : : array < type : : Viewport , type : : ViewportCount > > viewports ;
Register < 0x300 , std : : array < type : : ViewportClip , type : : ViewportCount > > viewportClips ;
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Register < 0x35B , type : : ClearRect > clearRect ;
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Register < 0x35D , u32 > vertexArrayStart ; //!< The first vertex to draw
struct DrawVertexArray {
u32 count ;
} ;
Register < 0x35E , DrawVertexArray > drawVertexArray ; //!< The amount of vertices to draw, calling this method triggers non-indexed drawing
Register < 0x35F , type : : ZClipRange > zClipRange ;
Register < 0x360 , std : : array < u32 , 4 > > colorClearValue ;
Register < 0x364 , float > zClearValue ;
Register < 0x368 , u32 > stencilClearValue ;
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Register < 0x36B , type : : PolygonMode > frontPolygonMode ;
Register < 0x36C , type : : PolygonMode > backPolygonMode ;
Register < 0x370 , type : : PolyOffset > polyOffset ;
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Register < 0x373 , u32 > patchSize ;
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Register < 0x380 , std : : array < type : : Scissor , type : : ViewportCount > > scissors ;
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struct DepthBiasEnable {
u32 point ; // 0x370
u32 line ; // 0x371
u32 fill ; // 0x372
} ;
Register < 0x370 , DepthBiasEnable > depthBiasEnable ;
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Register < 0x3D5 , type : : BackStencilValues > backStencilValues ;
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Register < 0x3D8 , u32 > tiledCacheEnable ;
struct TiledCacheSize {
u16 width ;
u16 height ;
} ;
Register < 0x3D9 , TiledCacheSize > tiledCacheSize ;
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Register < 0x3E4 , u32 > singleCtWriteControl ; //!< If enabled, the color write masks for all RTs must be set to that of the first RT
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Register < 0x3E7 , float > depthBoundsMin ;
Register < 0x3E8 , float > depthBoundsMax ;
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Register < 0x3EB , u32 > ctMrtEnable ;
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Register < 0x3F8 , Address > ztOffset ;
Register < 0x3FA , type : : ZtFormat > ztFormat ;
Register < 0x3FB , type : : ZtBlockSize > ztBlockSize ;
Register < 0x3FC , u32 > ztArrayPitch ;
Register < 0x3FD , type : : SurfaceClip > surfaceClip ;
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Register < 0x43E , type : : ClearSurfaceControl > clearSurfaceControl ;
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Register < 0x458 , std : : array < type : : VertexAttribute , type : : VertexAttributeCount > > vertexAttributes ;
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Register < 0x483 , u32 > invalidateSamplerCacheAll ;
Register < 0x484 , u32 > invalidateTextureHeaderCacheAll ;
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struct DrawVertexArrayBeginEndInstance {
u16 startIndex ;
u16 count : 12 ;
type : : DrawTopology topology : 4 ;
} ;
Register < 0x485 , DrawVertexArrayBeginEndInstance > drawVertexArrayBeginEndInstanceFirst ;
Register < 0x486 , DrawVertexArrayBeginEndInstance > drawVertexArrayBeginEndInstanceSubsequent ;
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Register < 0x487 , type : : CtSelect > ctSelect ;
Register < 0x48A , type : : ZtSize > ztSize ;
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struct DrawAuto {
u32 byteCount ;
} ;
Register < 0x48F , DrawAuto > drawAuto ;
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Register < 0x48D , type : : SamplerBinding > samplerBinding ; //!< If enabled, the TSC index in a bindless texture handle is ignored and the TIC index is used as the TSC index, otherwise the TSC index from the bindless texture handle is used
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Register < 0x490 , std : : array < u32 , 8 > > postVtgShaderAttributeSkipMask ;
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Register < 0x4B3 , u32 > depthTestEnable ;
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Register < 0x4B9 , u32 > blendStatePerTargetEnable ;
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Register < 0x4BA , u32 > depthWriteEnable ;
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Register < 0x4BB , u32 > alphaTestEnable ;
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struct InlineIndexAlign {
u32 count : 30 ;
u8 start : 2 ;
} ;
struct DrawInlineIndex {
u8 index0 ;
u8 index1 ;
u8 index2 ;
u8 index3 ;
} ;
Register < 0x4C1 , DrawInlineIndex > drawInlineIndex4X8 ;
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Register < 0x4C3 , type : : CompareFunc > depthFunc ;
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Register < 0x4C4 , float > alphaRef ;
Register < 0x4C5 , type : : CompareFunc > alphaFunc ;
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Register < 0x4C6 , u32 > drawAutoStride ;
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struct BlendConstant {
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float red ; // 0x4C7
float green ; // 0x4C8
float blue ; // 0x4C9
float alpha ; // 0x4CA
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} ;
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Register < 0x4C7 , std : : array < float , type : : BlendColorChannelCount > > blendConsts ;
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Register < 0x4CF , type : : Blend > blend ;
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Register < 0x4E0 , u32 > stencilTestEnable ;
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Register < 0x4E1 , type : : StencilOps > stencilOps ;
Register < 0x4E5 , type : : StencilValues > stencilValues ;
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Register < 0x4EB , type : : WindowOrigin > windowOrigin ;
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Register < 0x4EC , float > lineWidth ;
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Register < 0x4ED , float > lineWidthAliased ;
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Register < 0x50D , u32 > globalBaseVertexIndex ;
Register < 0x50E , u32 > globalBaseInstanceIndex ;
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Register < 0x544 , u32 > clipDistanceEnable ;
Register < 0x545 , u32 > sampleCounterEnable ;
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Register < 0x546 , float > pointSize ;
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Register < 0x547 , u32 > zCullStatCountersEnable ;
Register < 0x548 , u32 > pointSpriteEnable ;
Register < 0x54A , u32 > shaderExceptions ;
Register < 0x54D , u32 > multisampleEnable ;
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Register < 0x54E , type : : ZtSelect > ztSelect ;
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Register < 0x54F , type : : MultisampleControl > multisampleControl ;
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Register < 0x557 , TexSamplerPool > texSamplerPool ;
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Register < 0x55B , float > slopeScaleDepthBias ;
Register < 0x55C , u32 > aliasedLineWidthEnable ;
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Register < 0x55D , TexHeaderPool > texHeaderPool ;
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Register < 0x565 , u32 > twoSidedStencilTestEnable ; //!< Determines if the back-facing stencil state uses the front facing stencil state or independent stencil state
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Register < 0x566 , type : : StencilOps > stencilBack ;
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Register < 0x56F , float > depthBias ;
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Register < 0x57A , u32 > drawInlineIndex ;
struct InlineIndex2X16Align {
u32 count : 31 ;
bool startOdd : 1 ;
} ;
Register < 0x57B , InlineIndex2X16Align > inlineIndex2X16Align ;
struct DrawInlineIndex2X16 {
u16 even ;
u16 odd ;
} ;
Register < 0x57C , DrawInlineIndex2X16 > drawInlineIndex2X16 ;
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Register < 0x581 , type : : PointCoordReplace > pointCoordReplace ;
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Register < 0x582 , Address > programRegion ;
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Register < 0x585 , u32 > end ; //!< Method-only register with no real value, used after calling vertexBeginGl to invoke the draw
union Begin {
u32 raw ;
enum class PrimitiveId : u8 {
First = 0 ,
Unchanged = 1 ,
} ;
enum class InstanceId : u8 {
First = 0 ,
Subsequent = 1 ,
Unchanged = 2
} ;
enum class SplitMode : u8 {
NormalBeginNormalEnd = 0 ,
NormalBeginOpenEnd = 1 ,
OpenBeginOpenEnd = 2 ,
OpenBeginNormalEnd = 3
} ;
struct {
type : : DrawTopology op ;
u16 _pad0_ : 8 ;
PrimitiveId primitiveId : 1 ;
u8 _pad1_ : 1 ;
InstanceId instanceId : 2 ;
SplitMode splitMode : 4 ;
} ;
} ;
static_assert ( sizeof ( Begin ) = = sizeof ( u32 ) ) ;
Register < 0x586 , Begin > begin ; //!< Similar to glVertexBegin semantically, supplies a primitive topology for draws alongside instancing data
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Register < 0x591 , u32 > primitiveRestartEnable ;
Register < 0x592 , u32 > primitiveRestartIndex ;
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Register < 0x5A1 , type : : ProvokingVertex > provokingVertex ;
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Register < 0x5E7 , type : : ZtLayer > ztLayer ;
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Register < 0x5F2 , type : : IndexBuffer > indexBuffer ;
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struct DrawIndexBuffer {
u32 count ;
} ;
Register < 0x5F8 , DrawIndexBuffer > drawIndexBuffer ;
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struct DrawIndexBufferBeginEndInstance {
u16 first ;
u16 count : 12 ;
type : : DrawTopology topology : 4 ;
} ;
Register < 0x5F9 , DrawIndexBufferBeginEndInstance > drawIndexBuffer32BeginEndInstanceFirst ;
Register < 0x5FA , DrawIndexBufferBeginEndInstance > drawIndexBuffer16BeginEndInstanceFirst ;
Register < 0x5FB , DrawIndexBufferBeginEndInstance > drawIndexBuffer8BeginEndInstanceFirst ;
Register < 0x5FC , DrawIndexBufferBeginEndInstance > drawIndexBuffer32BeginEndInstanceSubsequent ;
Register < 0x5FD , DrawIndexBufferBeginEndInstance > drawIndexBuffer16BeginEndInstanceSubsequent ;
Register < 0x5FE , DrawIndexBufferBeginEndInstance > drawIndexBuffer8BeginEndInstanceSubsequent ;
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Register < 0x61F , float > depthBiasClamp ;
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Register < 0x620 , std : : array < type : : VertexStreamInstance , type : : VertexStreamCount > > vertexStreamInstance ; //!< A per-VBO boolean denoting if the vertex input rate should be per vertex or per instance
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Register < 0x646 , u32 > oglCullEnable ;
Register < 0x647 , type : : FrontFace > oglFrontFace ;
Register < 0x648 , type : : CullFace > oglCullFace ;
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Register < 0x649 , u32 > pixelCentreImage ;
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Register < 0x64B , u32 > viewportScaleOffsetEnable ;
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Register < 0x64F , type : : ViewportClipControl > viewportClipControl ;
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Register < 0x652 , type : : PrimitiveTopologyControl > primitiveTopologyControl ;
Register < 0x65C , type : : PrimitiveTopology > primitiveTopology ;
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Register < 0x66F , u32 > depthBoundsTestEnable ;
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Register < 0x671 , type : : LogicOp > logicOp ;
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Register < 0x674 , type : : ClearSurface > clearSurface ;
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Register < 0x680 , std : : array < type : : CtWrite , type : : ColorTargetCount > > ctWrites ;
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struct Semaphore {
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Address address ; // 0x6C0
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u32 payload ; // 0x6C2
type : : SemaphoreInfo info ; // 0x6C3
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} ;
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Register < 0x6C0 , Semaphore > semaphore ;
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Register < 0x700 , std : : array < type : : VertexStream , type : : VertexStreamCount > > vertexStreams ;
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Register < 0x780 , std : : array < type : : BlendPerTarget , type : : ColorTargetCount > > blendPerTargets ;
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Register < 0x7C0 , std : : array < Address , type : : VertexStreamCount > > vertexStreamLimits ; //!< A per-VBO IOVA denoting the end of the vertex buffer
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Register < 0x800 , std : : array < type : : Pipeline , type : : PipelineCount > > pipelines ;
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Register < 0x8C0 , u32 [ 0x20 ] > firmwareCall ;
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Register < 0x8E0 , type : : ConstantBufferSelector > constantBufferSelector ;
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/**
* @ brief Allows updating the currently selected constant buffer inline with an offset and up to 16 words of data
*/
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struct LoadConstantBuffer {
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u32 offset ;
std : : array < u32 , 16 > data ;
} ;
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Register < 0x8E3 , LoadConstantBuffer > loadConstantBuffer ;
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Register < 0x900 , std : : array < type : : BindGroup , type : : ShaderStageCount > > bindGroups ; //!< Binds constant buffers to pipeline stages
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Register < 0x982 , BindlessTexture > bindlessTexture ; //!< The index of the constant buffer containing bindless texture descriptors
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Register < 0xA00 , std : : array < std : : array < u8 , type : : StreamOutLayoutSelectAttributeCount > , type : : StreamOutBufferCount > > streamOutLayoutSelect ;
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} ;
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static_assert ( sizeof ( Registers ) = = ( EngineMethodsEnd * sizeof ( u32 ) ) ) ;
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# pragma pack(pop)
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private :
/**
* @ brief Writes back a semaphore result to the guest with an auto - generated timestamp ( if required )
* @ note If the semaphore is OneWord then the result will be downcasted to a 32 - bit unsigned integer
*/
void WriteSemaphoreResult ( const Registers : : Semaphore & semaphore , u64 result ) ;
public :
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Registers registers { } ;
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Registers shadowRegisters { } ; //!< A shadow-copy of the registers, their function is controlled by the 'shadowRamControl' register
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ChannelContext & channelCtx ;
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Maxwell3D ( const DeviceState & state , ChannelContext & channelCtx , MacroState & macroState ) ;
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/**
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* @ brief Initializes Maxwell 3 D registers to their default values
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*/
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void InitializeRegisters ( ) ;
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/**
* @ brief Flushes any batched constant buffer update or instanced draw state
*/
void FlushEngineState ( ) ;
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void CallMethod ( u32 method , u32 argument ) ;
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void CallMethodBatchNonInc ( u32 method , span < u32 > arguments ) ;
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void CallMethodFromMacro ( u32 method , u32 argument ) override ;
u32 ReadMethodFromMacro ( u32 method ) override ;
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void DrawInstanced ( u32 drawTopology , u32 vertexArrayCount , u32 instanceCount , u32 vertexArrayStart , u32 globalBaseInstanceIndex ) override ;
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void DrawIndexedInstanced ( u32 drawTopology , u32 indexBufferCount , u32 instanceCount , u32 globalBaseVertexIndex , u32 indexBufferFirst , u32 globalBaseInstanceIndex ) override ;
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void DrawIndexedIndirect ( u32 drawTopology , span < u8 > indirectBuffer , u32 count , u32 stride ) override ;
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} ;
}